• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.132-140
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• 2002

This paper presents an ARM-based SOC bus transaction verification IP and the usage experiences in SOC designs. The verification IP is an AMBA AHB protocol checker, which captures legal AHB transactions in FSM-style signal sequence checking routines. This checker can be considered as a reusable verification IP since it does not change unless the bus protocol changes. Our AHB protocol checker is designed to be scalable to any number of AHB masters and reusable for various AMBA-based SOC designs. The keys to the scalability and the reusability are Object-Oriented Programming (OOP), virtual port, and bind operation. This paper describes how OOP, virtual port, and bind features are used to implement AHB protocol checker. Using the AHB protocol checker, an AHB simulation monitor is constructed. The monitor checks the legal bus arbitration and detects the first cycle of an AHB transaction. Then it calls AHB protocol checker to check the expected AHB signal sequences. We integrate the AHB bus monitor into Verilog simulation environment to replace time-consuming visual waveform inspection, and it allows us to find design bugs quickly. This paper also discusses AMBA AHB bus transaction coverage metrics and AHB transaction coverage analysis. Test programs for five AHB masters of an SOC, four channel DMAs and a host interface unit are executed and transaction coverage for DMA verification is collected during simulation. These coverage results can be used to determine the weak point of test programs in terms of the number of bus transactions occurred and guide to improve the quality of the test programs. Also, the coverage results can be used to obtain bus utilization statistics since the bus cycles occupied by each AHB master can be obtained.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.629-638
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• 2005

In the System on a Chip design, the on chip bus is one of the critical factors that decides the overall system performance. Especially, in the case or reusing the IPs such as processors, DSPs and multimedia IPs that requires higher bandwidth, the bandwidth problems of on chip bus are getting more serious. Recently ARM proposes the Multi-Layer AHB BusMatrix that is a highly efficient on chip bus to solve the bandwidth problems. The Multi-Layer AHB BusMatrix allows parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. However, there is one clock cycle delay for each master in existing Multi-Layer AHB BusMatrix whenever the master starts new transactions or changes the slave layers because of the Input Stage and arbitration logic realized with Moore type. In this paper, we improved the existing Multi-Layer AHB BusMatrix architecture to solve the one clock cycle delay problems and to reduce the area overhead of the Input Stage. With the elimination of the Input Stage and some restrictions on the arbitration scheme, we tan take away the one clock cycle delay and reduce the area overhead. Experimental results show that the end time of total bus transaction and the average latency time of improved Multi-Layer AHB BusMatrix are improved by $20\%\;and\;24\%$ respectively. in ease of executing a number of transactions by 4-beat incrementing burst type. Besides the total area and the clock period are reduced by $22\%\;and\;29\%$ respectively, compared with existing Multi-layer AHB BusMatrix.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.36 no.5
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• pp.507-513
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• 2008

In this paper, we present a development of an Avionics Hot Bench(AHB) used for the verification of operational flight programs and fault analysis using various simulation and stimulation software. We propose an application of the open system architecture to develop the AHB which can be used for the development of a real aircraft avionics system. In the design of the AHB, to reduce the development period and cost we use as many as commercial off-the-shelf hardware and software items. The developed AHB is compared with the existing proven AHB which was used for T-50 avionics system development. Thorough comparison between the test results using the developed AHB and those using the existing AHB is performed and the overall comparison results are very satisfactory.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.553-555
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• 2004

SoC 분야에서 온 칩 버스는 전체 시스템의 성능을 결정하는 중요한 요소이다. 이에 따라 최근 ARM 사에서는 고성능 온 칩 버스 구조인 ML(Multi-Layer) AHB 버스를 제안하였다. ML AHB 버스는 저전력 임베디드 시스템에 적합한 버스 구조로써 현재 널리 사용되고 있다. 하지만, 고가이기 때문에 ADK(AMBA$^{TM}$ Design kit) 구매에 대한 부담이 적지 않다. 본 논문은 ML AHB의 버스 구조인 버스 매트릭스 구현 및 ADK에서 제공되지 않는 테스트 환경 즉, Protocol Checker 및 Performance Monitor Module 구현에 관한 것이다.

• Polymer(Korea)
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• v.39 no.1
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• pp.88-98
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• 2015

4-Amino-N-hexadecylbenzamide-graphene sheets (AHB-GSs), used in the preparation of the polyimide (PI) nanocomposite films, were synthesized by mixing a dispersion of graphite oxide with a solution of the ammonium salt of AHB. The atomic force microscope image of functionalized-GS on mica and a profile plot revealed the average thickness of AHB-GS to be ~3.21 nm. PI films were synthesized by reacting 4,4'-biphthalic anhydride and bis(4-aminophenyl) sulfide. PI nanocomposite films containing various contents of AHB-GS over the range of 0-10 wt% were synthesized using the solution intercalation method. The PI nanocomposite films under different thermal imidization temperatures, 250 and $350^{\circ}C$, were examined. The graphenes, for the most part, were well dispersed in the polymer matrix despite some agglomeration. However, micrometer-scale particles were not detected. The average thickness of the particles was <10 nm, as revealed from the transmission electron microscope images. Only a small amount of AHB-GS was required to improve the gas barrier, and electrical conductivity. In contrast, the glass transition and initial decomposition temperatures of the PI hybrid films continued to decrease with increasing content of AHB-GS up to 10 wt%. In general, the properties of the PI hybrid films heat treated at $350^{\circ}C$ were better than those of films heat treated at $250^{\circ}C$.

• ETRI Journal
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• v.28 no.3
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• pp.397-400
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• 2006

The multi-layer advanced high-performance bus (ML-AHB) BusMatrix proposed by ARM is an excellent architecture for applying embedded systems with low power. However, there is one clock cycle delay for each master in the ML-AHB BusMatrix of the advanced microcontroller bus architecture (AMBA) design kit (ADK) whenever a master starts new transactions or changes the slave layers. In this letter, we propose an improved design method to remove the one clock cycle delay in the ML-AHB BusMatrix of an ADK. We also remarkably reduce the total area and power consumption of the ML-AHB BusMatrix of an ADK with the elimination of the heavy input stages.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.33-37
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• 2013

In this paper, we introduce a SDRAM controller implemented on FPGA. Modern embedded system adopts SDRAM as a memory to meet the high capacity memory demands. Our SDRAM controller is written in Verilog and verified on an FPGA, demonstrating the functionality along with ARM Cortex-M0, supporting AMBA AHB.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.8
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• pp.554-561
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• 2006

In recent years, as SoC design research is actively conducted, a large number of IPs are included in a system. Various bus protocols and bus architectures are designed to increase IP reusability. Among them, the AMBA AHB became a de facto standard although it is somewhat inadequate for a large scale SoC. We proposed SNP and SNA, high performance on-chip-bus protocol and architecture, respectively, to solve the problem of the conventional shared buses. However, it seems to be imperative that the new on-chip-bus system support AMBA-compatible IPs for a while since there are a lot of IPs with AMBA interface. In this paper, we propose an extended SNP specification and a corresponding SNA component to support ABMA-compatible IPs used in SNA - based system. We extend the phase of the SNP by 1 bit to add new 8 phases to support communication based on AMBA protocol without penalty of elongated cycle latency. The ARB-to -XSNP converter translates the protocol between AHB and SNP to attach AMBA -compatible IPs to SNA based system. We show that AMBA IPs can communicate through SNP without any degradation of performance using the extended SNP and AHB - to- XSNP converter.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.919-921
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• 2004

최근 임베디드 시스템 설계에서 저전력 소모와 SoC가 주된 관심사가 되면서, ARM 프로세서와 AMBA 버스가 각광을 받고 있다. AMBA 버스가 고속 모듈에 대해서는 장점을 지니지만. 저속 모듈과의 인터페이스에는 많은 제약이 따른다. 따라서 속도가 서로 다른 이종 모듈간에 속도 보상을 위한 bridge 가 필요하다. 이러한 용도로 APB bridge가 표준으로 자리 매김하고 있지만, 속도가 고정되어 있기 때문에 융통성이 배제된다. 본 논문에서는 이러한 단정을 보완하기 위해, 구조가 간단하고 구현이 쉬운 ISA 방식의 bridge를 제안하여, 많은 주변장치들을 손쉽게 AHB Slave로 인터페이스 할 수 있게 만든다.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.527-528
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• 2008

In this paper, several cases of multi-shared bus architecture are discussed and in order to decrease the bridge latency, the architecture introducing a memory decoder is proposed. Finally, a LCD controller using DMA master is integrated in this bus architecture that is verified due to RTL simulation and FPGA board test. DMA, LCD line buffer and SDRAM controller are normally operated in the timing simulation using ModelSim tool, and the LCD image is confirmed in the real FPGA board containing LCD panel.