• Title/Summary/Keyword: AES Encryption

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Area-Optimized Multi-Standard AES-CCM Security Engine for IEEE 802.15.4 / 802.15.6

  • Choi, Injun;Kim, Ji-Hoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.3
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    • pp.293-299
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    • 2016
  • Recently, as IoT (Internet of Things) becomes more important, low cost implementation of sensor nodes also becomes critical issues for two well-known standards, IEEE 802.15.4 and IEEE 802.15.6 which stands for WPAN (Wireless Personal Area Network) and WBAN (Wireless Body Area Network), respectively. This paper presents the area-optimized AES-CCM (Advanced Encryption Standard - Counter with CBC-MAC) hardware security engine which can support both IEEE 802.15.4 and IEEE 802.15.6 standards. First, for the low cost design, we propose the 8-bit AES encryption core with the S-box that consists of fully combinational logic based on composite field arithmetic. We also exploit the toggle method to reduce the complexity of design further by reusing the AES core for performing two operation mode of AES-CCM. The implementation results show that the total gate count of proposed AES-CCM security engine can be reduced by up to 42.5% compared to the conventional design.

An AES-GCM Crypto-core for Authenticated Encryption of IoT devices (IoT 디바이스의 인증암호를 위한 AES-GCM 암호코어)

  • Sung, Byung-Yoon;Kim, Ki-Bbeum;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2017.10a
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    • pp.253-255
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    • 2017
  • 본 논문에서는 IoT 디바이스의 인증암호를 위한 AES-GCM 암호코어를 설계하였다. AES-GCM 코어는 블록암호 AES와 GHASH 연산으로 기밀성과 무결성을 동시에 제공한다. 기밀성 제공을 위한 블록암호 AES는 운영모드 CTR과 비밀키 길이 128/256-bit를 지원한다. GHASH 연산과 AES 암호화(복호화)의 병렬 동작을 위해 소요 클록 사이클을 일치시켜 GCM 동작을 최적화 하였다. 본 논문에서는 AES-GCM 코어를 Verilog HDL로 모델링 하였고 ModelSim을 이용한 시뮬레이션 검증 결과 정상 동작함을 확인하였으며 Xilinx Virtex5 XC5VSX95T FPGA 디바이스 합성결과 4,567 슬라이스로 구현되었다.

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An Efficient Implementation of AES Encryption Algorithm for CCTV Image Security (CCTV 영상보안 위한 AES 암호 알고리듬의 효율적인 구현)

  • Kang, Min-Sup
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.21 no.2
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    • pp.1-6
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    • 2021
  • In this paper, an efficient implementation of AES encryption algorithm is presented for CCTV image security using C# language. In this approach, an efficient S-Box is first designed for reducing the computation time which is required in each round process of AES algorithm, and then an CCTV image security system is implemented on the basis of this algorithm on a composite field GF(((22)2)2). In addition, the shared S-Box structure is designed for realizing the minimized memory space, which is used in each round transformation and key scheduling processes. Through performance evaluation, it was confirmed that the proposed method is more efficient than the existing method. The proposed CCTV system in C# language using Visual studio 2010.

Analysis of Implementation and Performance of LEA Algorithm for Server Environment (서버환경에서의 LEA 암호 알고리즘 구현 및 성능분석)

  • Yun, Chae-won;Lee, Jaehoon;Yi, Okyoen
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2014.10a
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    • pp.359-362
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    • 2014
  • With recent growing of application service, servers are required to sustain great amount of data and to handle them quickly: besides, data must be processed securely. The main security algorithm used in security services of server is AES(Advanced Encryption Standard - 2001 published by NIST), which is widely accepted in the world market for superiority of performance. In Korea, NSRI(National Security Research Institute) has developed ARIA(Academy, Research Institute, Agency) algorithm in 2004 and LEA(Lightweight Encryption Algorithm) algorithm in 2012. In this paper, we show advantage of LEA by comparing performance with AES and ARIA in various servers.

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Formal Verification of AES Encryption Module Using CBMC (CBMC를 이용한 AES 암호화 모듈의 정형 검증)

  • Ahn Young-Jung;Choi Jin-Young
    • Proceedings of the Korean Information Science Society Conference
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    • 2005.11a
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    • pp.97-99
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    • 2005
  • 정보보호 제품의 주요한 역할을 담당하는 암호 모듈의 구현 무결성을 보증하기 위해 많은 연구가 활발히 이루어지고 있다. 하지만 기존의 일반적인 테스팅 방법으로는 구현 무결성에 대해 신뢰하지 못한다. 본 논문에서는 NIST (the US National Institute of Science and Technology)에서 AES(Advanced Encryption Standard)로 제정된 Rijndael 블록암호 모듈을 Verilog로 구현하고 CBMC를 이용하여 새로운 방식의 구현 무결성 평가 방법을 제시하고자 한다.

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The Design and Implementation of AES-128 Rijndael Cipher Algorithm (AES-128 Rijndael 암ㆍ복호 알고리듬의 설계 및 구현)

  • 신성호;이재흥
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.7
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    • pp.1478-1482
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    • 2003
  • In this paper. Rijndael cipher algorithm is implemented by a hardware. It was selected as the AES(Advanced Encryption Standard) by NIST. It has structure that round operation divided into 2 subrounds and subrounds are pipelined to calculate efficiently. It takes 5 clocks for one-round. The AES-128 cipher algorithm is implemented for hardware by ALTERA FPGA, and, analyzed the performance. The AES-128 cipher algorithm has approximately 424 Mbps encryption rate for 166Mhz max clock frequency. In case of decryption, it has 363 Mbps decryption rate fu 142Mhz max clock frequency. In case of cipher core, it has 320Mbps encryptionㆍdecryption rate for 125Mhz max clock frequency.

Modified AES having same structure in encryption and decryption (암호와 복호가 동일한 변형 AES)

  • Cho, Gyeong-Yeon;Song, Hong-Bok
    • Journal of Korea Society of Industrial Information Systems
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    • v.15 no.2
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    • pp.1-9
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    • 2010
  • Feistel and SPN are the two main structures in a block cipher. Feistel is a symmetric structure which has the same structure in encryption and decryption, but SPN is not a symmetric structure. In this paper, we propose a SPN which has a symmetric structure in encryption and decryption. The whole operations of proposed algorithm are composed of the even numbers of N rounds where the first half of them, 1 to N/2 round, applies a right function and the last half of them, (N+1)/2 to N round, employs an inverse function. And a symmetry layer is located in between the right function layer and the inverse function layer. In this paper, AES encryption and decryption function are selected for the right function and the inverse function, respectively. The symmetric layer is composed with simple matrix and round key addition. Due to the simplicity of the symmetric SPN structure in hardware implementation, the proposed modified AES is believed to construct a safe and efficient cipher in Smart Card and RFID environments where electronic chips are built in.

Dual encryption technique for lightweight encryption communication (경량 암호화 통신을 위한 이중암호화 기법)

  • Heegyung Bae;Hye Yeon Shim;Il-Gu Lee
    • Annual Conference of KIPS
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    • 2024.05a
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    • pp.308-309
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    • 2024
  • IoT(Internet of Things) 기기를 대상으로 하는 보안 위협이 증가하면서 IoT 정보의 기밀성 유지가 중요한 과제로 떠오르고 있다. 따라서 경량, 저가, 저전력 IoT 환경에서 높은 보안 수준을 유지할 수 있는 암호화 방법이 필요하다. 본 연구에서 AES(Advanced Encryption Standard)와 SAES(Simplified AES)를 이용한 이중 암호화 기법을 제안한다. 제안하는 기법은 SAES 로 평문 메시지 전체를 블록 단위로 암호화하고, 각 암호문 블록의 일부 비트를 추출해 AES 로 재암호화한다. 실험 결과에 따르면, 제안한 경량 이중 암호화 기법이 종래 방식보다 암호문의 크기를 32% 줄일 수 있었다.

A Design of AES-based WiBro Security Processor (AES 기반 와이브로 보안 프로세서 설계)

  • Kim, Jong-Hwan;Shin, Kyung-Wook
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.7 s.361
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    • pp.71-80
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    • 2007
  • This paper describes an efficient hardware design of WiBro security processor (WBSec) supporting for the security sub-layer of WiBro wireless internet system. The WBSec processor, which is based on AES (Advanced Encryption Standard) block cipher algorithm, performs data oncryption/decryption, authentication/integrity, and key encryption/decryption for packet data protection of wireless network. It carries out the modes of ECB, CTR, CBC, CCM and key wrap/unwrap with two AES cores working in parallel. In order to achieve an area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented using field transformation technique. It results that the gate count of WBSec is reduced by about 25% compared with conventional LUT (Look-Up Table)-based design. The WBSec processor designed in Verilog-HDL has about 22,350 gates, and the estimated throughput is about 16-Mbps at key wrap mode and maximum 213-Mbps at CCM mode, thus it can be used for hardware design of WiBro security system.

The fast image encryption algorithm based on substitution and diffusion

  • Zhang, Yong;Jia, Xiaoyang
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.12 no.9
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    • pp.4487-4511
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    • 2018
  • A fast image encryption system based on substitution and diffusion was proposed, which includes one covering process, one substitution process and two diffusion processes. At first, Chen's chaotic system together with an external 256-bit long secret key was used to generate the key streams for image encryption, in which the initial values of Chen's chaotic system were regarded as the public key. Then the plain image was masked by the covering process. After that the resulting image was substituted with the disturbed S-Box of AES. Finally, the substituted image was diffused twice with the add-modulo operations as the core to obtain the cipher image. Simulation analysis and comparison results with AES and some existing image cryptosystems show that the proposed image cryptosystem possesses the merits of fast encryption/decryption speed, good statistical characteristics, strong sensitivity and etc., and can be used as a candidate system of network security communication.