• Journal of the Korea Society of Computer and Information
• /
• v.17 no.2
• /
• pp.113-118
• /
• 2012

In this paper, we discuss the design of the Digital Down Converters for the IEEE 802.11 wireless LAN receiver, which can be used for the customized receiver. The customized receiver can be used for special puropsed services which cannot be realized using the general custom chip. In the OFDM receiver, DDC receives the up sampled Inphase/Quadrature signal from the AD converter and process down sampling and filtering procedures using the Cascaded Intergrator Filter and FIR filters. We discuss the structure and design methodology of DDC's and analyze the simulation results.

• Journal of Power Electronics
• /
• v.16 no.6
• /
• pp.2212-2220
• /
• 2016

Based on the conventional PID algorithm and the adaptive PID (AD-PID) algorithm, a separate sampling adaptive PID (SSA-PID) algorithm is proposed to improve the transient response of digitally controlled DC-DC converters. The SSA-PID algorithm, which can be divided into an oversampled adaptive P (AD-P) control and an adaptive ID (AD-ID) control, adopts a higher sampling frequency for AD-P control and a conventional sampling frequency for AD-ID control. In addition, it can also adaptively adjust the PID parameters (i.e. $K_p$, $K_i$ and $K_d$) based on the system state. Simulation results show that the proposed algorithm has better line transient and load transient responses than the conventional PID and AD-PID algorithms. Compared with the conventional PID and AD-PID algorithms, the experimental results based on a FPGA indicate that the recovery time of the SSA-PID algorithm is reduced by 80% and 67% separately, and that overshoot is decreased by 33% and 12% for a 700mA load step. Moreover, the SSA-PID algorithm can achieve zero overshoot during startup.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.2
• /
• pp.1023-1026
• /
• 2005

본 논문에서는 SDR(Software Defined Radio) 시스템을 위한 Digital IF(Intermediate Frequency) Up/Down 변환기를 설계하고 성능을 평가하였다. 설계한 시스템은 AD 변환부, DA 변환부 및 Up-Down conversion 기능을 수행하는 FPGA로 구성된다. AD 변환부는 Analog Device 사의 AD6645를 사용하였으며, DA 변환부는 Analog Device 사의 AD9775를 사용하였다. Up-Down conversion 기능을 수행하는 FPGA부는 샘플된 IF 입력을 혼합기와 NCO에 의해 기저대역(DC)으로 다운 시키는 역할을 하며, 14bit의 기저대역(DC) 신호를 혼합기와 NCO에 의해 IF 출력으로 올려주는 역할을 한다. 이러한 설계는 기존의 아날로그 헤테로다인 방식에 비하여 높은 유연성 및 우수한 성능 향상을 보여준다.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.549-550
• /
• 2008

This paper proposed and designed the modified flash analog-to-digital converter(ADC). The speed of new architecture is similar to conventional flash ADC but the die area consumption is much less due to reduce numbers of comparators. The circuits which are implemented in this paper is simulated with LT SPICE and layout with Electric tools of computer.

• Journal of Broadcast Engineering
• /
• v.21 no.5
• /
• pp.803-815
• /
• 2016

In this paper, we design a direct radio frequency (RF) sampling receiver for multiband GNSS signals and demonstrate its performance. The direct RF sampling is a technique that does not use an analog mixer, but samples the passband signal directly, and all receiver processes are done in digital domain, whereas the conventional intermediate frequency (IF) receiver samples the IF band signals. In contrast to the IF sampling receiver, the RF sampling receiver is less complex in hardware, reconfigurable, and simultaneously converts multiband signals to digital signals with an analog-to-digital (AD) converter. The reconfigurability and simultaneous reception are very important in military applications where rapid change to other system is needed when a system is jammed by an enemy. For simultaneous reception of multiband signals, the sampling frequency should be selected with caution by considering the carrier frequencies, bandwidths, desired intermediate frequencies, and guard bands. In this paper, we select a sampling frequency and design a direct RF sampling receiver to receive multiband global navigation satellite system (GNSS) signals such as GPS L1, GLONASS G1 and G2 signals. The receiver is implemented with a commercial AD converter and software. The receiver performance is demonstrated by receiving the real signals.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.11B
• /
• pp.1895-1902
• /
• 2000

이 논문에서는 AD 변화기의 앞에 설치되는 샘플-앤드-홀드 회로의 비선형성을 보상하기 위해 신경 회로망 기법과 볼테라 급수 모델을 직접적으로 적용하는 기법을 제안한다. 제안하는 기법들의 성능을 비교하기 위해, 볼테라 급수 모델에 기반을 둔 전통적인 p차 역산 방식의 결과와 비교 검토한다. 비교 검토를 위해서는 모노-톤과 투-톤 신호를 사용하여 출력의 고조파 및 혼변조 레벨을 살펴보았다. p차 역산 방식이 역 시스템을 구하는 것이라면 제안하는 기법들은 최적화 기법에 바탕을 두고 있다고 할 수 있다. 결과를 보면 어떤 한 방식이 다른 방식보다 성능이 월등하다고 할 수 없는데, 그 이유는 각 방식마다 나름대로의 장단점을 갖고 있기 때문이다. 보상 방식의 선택은 신호의 통계적 성질, 신호 레벨, 비선형성의 정도 등을 고려해야 한다.

• Journal of Sensor Science and Technology
• /
• v.13 no.1
• /
• pp.35-40
• /
• 2004

A thin-film multijunction thermal converter was fabricated through the process using 6 inch silicon wafer semiconductor process and bulk micromachining. Evanohm R alloy and chromel-constantan were used as a heater and thermocouple materials, respectively. The temperature coefficient of resistance of Evanohm R heater was about 75.12 ppm/$^{\circ}C$ and the voltage sensitivity of the thermal converter indicated about 5.75 mV/mW in air. The transfer differences, measured by FRDC-DC method in the frequency range from 20 Hz to 10 kHz, showed the value under about 1.36 ppm, 0.83 ppm for the film thickness of 500, 200 nm, respectively. And in case of a 200 nm-thick thermal converter, the AC-DC transfer differences seems to be stabilized below the value of 1 ppm in the frequency range from 1 kHz to 500 kHz.

• Proceedings of the KIPE Conference
• /
• 2002.07a
• /
• pp.378-381
• /
• 2002

This paper describes a novel multilevel ad/dc power converter suitable for the protection of frequent output short-circuit. The output dc power of the proposed converter can be disconnected from the load within several hundred microseconds at the instant of short-circuit fault. The rising time of the dc load voltage is as small as several hundred microseconds, and there is no overshoot of the do voltage because the dc output capacitors keep undischarged state. Analysis and simulations are carried out to investigate the operation and usefulness of the proposed scheme.

• Journal of the Semiconductor & Display Technology
• /
• v.13 no.4
• /
• pp.71-76
• /
• 2014

This paper presents the implementation for the BLDC motor speed control system using VHDL and FPGA. The BLDC motor is widely used in automation for its good robustness and easy controllability. In order to control the speed of the BLDC motor, the PI controller used for static RPM output of the BLDC motor to variations in load. In addition, by using the DA converter, we were able to monitor the BLDC motor reference speed and the current speed through real time. The motor speed command and the parameters of the PI speed controller were modified easily by the FPGA and the AD converter. Finally, in order to show the feasibility of the control algorithm the speed control characteristics of the motor was monitored using an oscilloscope and the DA converter. Further, the speed control system was designed in this paper has shown the applicability of the drive system of the factory automation.

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2009.05a
• /
• pp.255-256
• /
• 2009

The anti suck back centering (ASBC) for preventing backflow of oil for oil rotary pump was designed in the power failure. To evaluate the evacuation characteristics, we manufactured the mini vacuum system, personal computer, AD converter (National instrument, NI-6009), and automatic controller with touch panel for a basis. In this study, we measured the evacuation characteristics of ABSC and analyzed the flow field of viscous flow regime using a commercial software, CFD-ACE+. Also, the leakage of the advaced ASBC for leveling was measured.