• 한국정보통신학회논문지
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• 제12권2호
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• pp.282-289
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• 2008

PDP TV의 전력 효율을 향상시키기 위해서는 PDP의 구동과정에서 발생하게 되는 불필요한 전력소모와 AC 입력으로부터 원하는 DC를 얻기 위한 과정 중에 발생하는 전력 소모를 최소화하여야 한다. 일반적인 PDP 구동을 위한 입력 전원단은 2단 구조의 역률 보상형 컨버터를 채용하고 있으며, PDP 구동시 전력소모가 가장 큰 서스테인 드라이버와 리셋 회로의 구동전원을 공급하기 위한 별도의 DC-to-DC 컨버터를 필요로 한다. 그러나 이러한 회로의 구현은 저가의 PDP를 요구하는 시장 상황에 유연하게 대처하는데 많은 어려움을 준다. 따라서 본 논문에서는 최소의 전력 변환단계를 가지도록 서스테인과 리셋 회로의 전원 공급이 가능한 1단방식의 역률보상형 AC-to-DC 컨버터를 제안한다. 제안하는 시스템은 1단방식의 입력전원부 구성을 통해 전력 변환단을 최소화하여 전력 변환 중에 발생하는 손실을 최소화하며, PDP 서스테인/리셋 드라이버의 구동전압을 직접 공급하는 형태로 구성하여 시스템 부피의 감소, 원가 절감을 이룰 수 있다.

• 반도체디스플레이기술학회지
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• 제12권2호
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• pp.45-50
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• 2013

This paper focuses on the fundamental issues for improving the efficiency and throughput of the AC PDP (Plasma Display Panel) manufacturing. The properties of the MgO protective layer affect the PDP efficiency. Especially, the secondary electron emission efficiency was affected on the deposition rate of MgO during the evaporation. In this study, the deposition rate of 5 $\AA$/s has given the maximum efficiency value of 0.05 It is demonstrated that the impurity gases such as $H_2O$, $CO_2$, CO or $N_2$, and $O_2$ can be remained inside the PDP panel before sealing and the amount of the impurity gases decreased rapidly as the base vacuum level increased, especially near $10^{-5}$ torr. The fundamental solution in order to overcome these problems is the vacuum in-line sealing process from the MgO evaporation to the final sealing of the panel without breaking the vacuum. We have demonstrated this fundamental process technology and shown the feasibility. The firing voltage was reduced down to 285 V at the base vacuum value of $10^{-6}$ torr, whreras it was about 328 V at the base vacuum value of $10^{-3}$ torr.

• 한국전기전자재료학회논문지
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• 제25권12호
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• pp.1004-1008
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• 2012

The effect of address discharge characteristics by selective reset method is investigated to prevent the weakness of address discharge in the middle of a TV-field without increase of the black luminance. To reduce black luminance in AC PDP usually, the first subfield during one TV frame adopted the conventional rising ramp-reset waveform, whereas the other subfields adopted the subsidiary reset waveform without rising ramp type. As the wall charge for the address discharge was accumulated by only the rising ramp waveform during the first reset period, the wall charge on three electrodes was disappeared as time passed and the address discharge would be weakened in the rear subfields. To prevent a reduction of the address discharge characteristics without decrease the black luminance, the modified rising ramp reset waveform was adopted only in the sixth subfield. As a result, a modified driving method could improve the address discharge characteristics compared with selective reset driving scheme with almost the same black luminance.

• 전기학회논문지
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• 제56권9호
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• pp.1619-1625
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• 2007

The gas mixture ratio of PDP discharges plays a very important role in the discharge characteristics of a plasma display panel. The increase of Xe contents results in the increases of luminance and luminous efficiency while it also results in the increase of the breakdown voltage. The addition of He gas increases the brightness and the luminous efficiency. Especially, the luminance and the luminous efficiency have a maximum value when the partial pressure of He is about 10% of the total pressure for a standard plasma display panel with Xe fraction of $10\sim30%$.

• 전기학회논문지
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• 제56권3호
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• pp.577-582
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• 2007

The plasma display panel is an image expression display using gas discharge plasma. However, gas discharge characteristics vary with temperature as gas discharge is sensitive to temperature. The discharge time lag extends a lot in low temperature and it is known as the cause which hinders high speed addressing which is essential for the size enlargement of the panel. Accordingly this research aims at identifying the temperature-dependent discharge characteristic. The lower temperature becomes, the longer addressing discharge time lag becomes. Particularly the statistical time lag extends much in low temperature. The increasing of electric field shortens discharge time lag in low temperature. Also, when priming particles are sufficiently supplied, stable discharge can be performed regardless of the influence of temperature.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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• pp.183-184
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• 2000

A new driving circuit for scan electrode in AC PDP has been developed. The number of scan driver switches can be reduced to one half of the conventional circuit. Capacitance between the electrodes is utilized. Experiments and analysis of the new structure has been carried out to confirm its robustness.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권12호
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• pp.606-615
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• 2004

The discharge characteristics of a ramp reset waveform in the alternating current plasma display panel(ac PDP) were studied using a 2-dimensional numerical simulation. We analyzed the wall charge variation during the reset discharge, address discharge and sustain discharge adopting a ramp reset waveform. Then we investigated the principal parameters for a successful discharge. In this paper, we suggest a new parameter, printing particles' density and its effects on the stability of the ramp discharge. The maximum current flows of the three electrodes during the ramp reset period were decreased with the increase in the priming particles's density which was explained with the wall charge characteristics and the current flow characteristics obtained by a 2-D simulation.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제51권11호
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• pp.541-545
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• 2002

This paper proposes the new narrow erase method to erase wall charges formed in an AC plasma display panel (PDP) cell. In the proposed method, pulse timing of switch at the sustain period is adjusted for inducing, a weak discharge. Then, after the narrow erase, the voltage of the X electrode is set to differ from that of the Y electrode. For the proposed method, the measured maximum address voltage margin was 38.3V at Y_Rest voltage of 100V and sustain voltage of 180${\sim}$185V. However, for the conventional method, in which the X and Y electrodes are set to be of equal voltage after the narrow erase, the measured maximum address voltage margin was 31.3V at Y_Rest voltage of 150V and sustain voltage of 180V. This result shows that the measured maximum voltage margin for the proposed method is about 7V(22%) higher than that for the conventional method.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 추계학술대회 논문집 학회본부
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• pp.379-381
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• 1997

The dielectric layers in AC plasma display panel(AC PDP) are essential to the discharge cell structure, because they protect metal electrodes from sputtering by positive ion and from a sheath of wall charges which are essential to memory function of AC PDP. Furthermore, this layer should be transparent because the visible light must pass through the layer. In this paper, the dielectric breakdown strength and transparency of the dielectric layer on the discharge electrodes are studied. The variables in this test are the dielectric layer thickness, dielectric firing condition, gas pressure, species of gas and so on.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.106-106
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• 2010

AC PDP(Plasma Display Panel)는 상압에 가까운 압력에서 DBD(Dielectric Barrier Discharge) 방전을 이용한 디스플레이다. AC PDP는 보통 면 방전을 이용하기 때문에 대향 방전과는 다른 방전 현상을 보인다. 본 연구에서는 4인치 test 패널 제작하여 격벽 높이 변화에 따른 방전 현상을 연구하였다. PDP 셀은 $1mm^3$ 보다 작은 크기를 가지고 있기 때문에 방전 현상을 분석하는 것은 쉽지 않다. 그래서 이 연구에서는 2, 3차원 유체 시뮬레이션을 이용하여 실험 결과에 대한 방전 현상을 연구하였다. 테스트 패널을 통하여 정적 마진, 휘도, 소비전력, 발광효율 등을 구하였고, Fluid 시뮬레이션을 통하여 전기장 분포, 하전입자 및 여기종 입자들의 개수 및 밀도 분포, 벽전하 분포 등을 통하여 방전 특성의 경향성을 분석하였다. 격벽 높이가 높아질수록 방전 공간이 넓어지면서 효율이 증가하였으나 $140\;{\mu}m$ 이상의 높이에서는 광 변환 효율이 감소하면서 효율이 오히려 감소하였다.