• Title/Summary/Keyword: A Boolean function

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Optimization of $\mu$0 Algorithm for BDD Minimization Problem

  • Lee, Min-Na;Jo, Sang-Yeong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.2
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    • pp.82-90
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    • 2002
  • BDD have become widely used for various CAD applications because Boolean functions can be represented uniquely and compactly by using BDD. The size of the BDD representation for a function is very sensitive to the choice of orderings on the input variable. Therefore, it is very important to find a good variable ordering which minimize the size of the BDD. Since finding an optimal ordering is NP-complete, several heuristic algorithms have been proposed to find good variable orderings. In this paper, we propose a variable ordering algorithm, Faster-${\mu}$0, based on the ${\mu}$0(microcanonical optimization). In the Faster-${\mu}$0 algorithm, the initialization phase is replaced with a shifting phase to produce better solutions in a fast local search. We find values for algorithm parameters experimentally and the proposed algorithm has been experimented on well known benchmark circuits and shows superior performance compared to various existing algorithms.

A Selection-Deletion of Prime Implicants Algorithm Based on Frequency for Circuit Minimization (빈도수 기반 주 내포 항 선택과 삭제 알고리즘을 적용한 회로 최소화)

  • Lee, Sang-Un
    • Journal of the Korea Society of Computer and Information
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    • v.20 no.4
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    • pp.95-102
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    • 2015
  • This paper proposes a simple algorithm for circuit minimization. There are currently two effective heuristics for circuit minimization, namely manual Karnaugh maps and computable Quine-McCluskey algorithm. The latter, however, has a major defect: the runtime and memory required grow $3^n/n$ times for every increase in the number of variables n. The proposed algorithm, however, extracts the prime implicants (PI) that cover minterms of a given Boolean function by deriving an implicants table based on frequency. From a set of the extracted prime implicants, the algorithm then eliminates redundant PIs again based on frequency. The proposed algorithm is therefore capable of minimizing circuits polynomial time when faced with an increase in n. When applied to various 3-variable and 4-variable cases, it has proved to swiftly and accurately obtain the optimal solutions.

A Simple Connection Pruning Algorithm and its Application to Simulated Random Signal Classification (연결자 제거를 위한 간단한 알고리즘과 모의 랜덤 신호 분류에의 응용)

  • Won, Yong-Gwan;Min, Byeong-Ui
    • The Transactions of the Korea Information Processing Society
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    • v.3 no.2
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    • pp.381-389
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    • 1996
  • A simple modification of the standard back-propagation algorithm to eliminate redundant connections(weights and biases) is described. It was motivated by speculations from the distribution of the magnitudes of the weights and the biases, analysis of the classification boundary, and the nonlinearity of the sigmoid function. After initial training, this algorithm eliminates all connections of which magnitude is below a threshold by setting them to zero. The algorithm then conducts retraining in which all weights and biases are adjusted to allow important ones to recover. In studies with Boolean functions, the algorithm reconstructed the theoretical minimum architecture and eliminated the connections which are not necessary to solve the functions. For simulated random signal classification problems, the algorithm produced the result which is consistent with the idea that easier problems require simpler networks and yield lower misclassification rates. Furthermore, in comparison, our algorithm produced better generalization than the standard algorithm by reducing over fitting and pattern memorization problems.

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Test Generation for Partial Scanned Sequential Circuits Based on Boolean Function Manipulation (논리함수처리에 의한 부분스캔순차회로의 테스트생성)

  • Choi, Ho-Yong
    • The Transactions of the Korea Information Processing Society
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    • v.3 no.3
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    • pp.572-580
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    • 1996
  • This paper describes a test generation method for sequential circuits which improves the application limits of the IPMT method by applying the partial scan design to the IPMT method. To solve the problem that the IPMT method requires enormous computation time in image computation, and generates test patterns after the partialscan design is introduced to reduce test complexity. Scan flip-flops are selected for the partial scan design according to the node size of the state functions of a sequential circuit in their binary decision diagram representations. Experimental results on ISCAS'95 benchmark circuits show that a test generator based on our method has achieved 100% fault coverage by use of either 20% scan FFs for s344, s349, and s420 or 80% scan FFs for sl423. However, test gener-ators based on the previous IPM method have not achieved 100% fault coverage for those circuits.

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On Implementations of Algorithms for Fast Generation of Normal Bases and Low Cost Arithmetics over Finite Fields (유한체위에서 정규기저의 고속생성과 저비용 연산 알고리즘의 구현에 관한 연구)

  • Kim, Yong-Tae
    • The Journal of the Korea institute of electronic communication sciences
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    • v.12 no.4
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    • pp.621-628
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    • 2017
  • The efficiency of implementation of the arithmetic operations in finite fields depends on the choice representation of elements of the field. It seems that from this point of view normal bases are the most appropriate, since raising to the power 2 in $GF(2^n)$ of characteristic 2 is reduced in these bases to a cyclic shift of the coordinates. We, in this paper, introduce our algorithm to transform fastly the conventional bases to normal bases and present the result of H/W implementation using the algorithm. We also propose our algorithm to calculate the multiplication and inverse of elements with respect to normal bases in $GF(2^n)$ and present the programs and the results of H/W implementations using the algorithm.

Design of 3-bit Arbitrary Logic Circuit based on Single Layer Magnetic-Tunnel-Junction Elements (단층 입력 구조의 Magnetic-Tunnel-Junction 소자를 이용한 임의의 3비트 논리회로 구현을 위한 자기논리 회로 설계)

  • Lee, Hyun-Joo;Kim, So-Jeong;Lee, Seung-Yeon;Lee, Seung-Jun;Shin, Hyung-Soon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.12
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    • pp.1-7
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    • 2008
  • Magnetic Tunneling Junction (MTJ) has been used as a nonvolatile universal storage element mainly in memory technology. However, according to several recent studies, magneto-logic using MTJ elements show much potential in substitution for the transistor-based logic device. Magneto-logic based on MTJ can maintain the data during the power-off mode, since an MTJ element can store the result data in itself. Moreover, just by changing input signals, the full logic functions can be realized. Because of its programmability, it can embody the reconfigurable magneto-logic circuit in the rigid physical architecture. In this paper, we propose a novel 3-bit arbitrary magneto-logic circuit beyond the simple combinational logic or the short sequential one. We design the 3-bit magneto-logic which has the most complexity using MTJ elements and verify its functionality. The simulation results are presented with the HSPICE macro-model of MTJ that we have developed in our previous work. This novel magneto-logic based on MTJ can realize the most complex logic function. What is more, 3-bit arbitrary logic operations can be implemented by changing gate signals of the current drivel circuit.