• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.47 no.2
• /
• pp.35-42
• /
• 2010

In this study, crosstalk between dominant interconnect pairs in an A/D converter circuit is analyzed in frequency domain and effects of termination conditions on crosstalk are described, based on the practical circuit conditions. An A/D converter circuit is a mixed circuit where both clean and noisy signals coexist such that the circuit probably suffers from distortion by crosstalk. An analog input signal and the reference voltage signal, which dominate the overall conversion performance of the A/D converter circuit, are ready to be distorted by crosstalk and include specific termination conditions, such as non-matching and capacitive termination, respectively. Thus, this study presents the model of crosstalk considering impedance mismatch at both ends and analyzes effects of the practical termination conditions in the analog input and the reference voltage interconnects on crosstalk. A typical circuit configuration of the two interconnects is described and crosstalk including near-end and far-end termination impedances is modeled. Effects of the near-end impedance mismatch in the analog input interconnect and the far-end capacitive termination in the reference voltage interconnect are estimated in the frequency domain by using the model of crosstalk and experiments are performed to confirm the estimated results. Microstrip lines are used as interconnects, involving the increase of loss in high frequencies.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.263-266
• /
• 1999

In this work, a A/D converter is implemented to obtain 8bit resolution at a conversion rate of 10MS/s for video applications. This architecture is proposed using the Pipelined architecture for high speed conversion rate and the Successive - Approximation architecture for low power consumption, and consists of two identical stages that consist of sample/hold circuit, low power comparator, voltage reference circuit and MDAC of binary weighted capacitor array. Proposed A/D converter is designed using 0.25${\mu}{\textrm}{m}$ CMOS technology The SNR is 80㏈ at a sampling rate of 10MHz with 1.95MHz sine input signal. When an 8bit 10MS/s A/D converter is simulated, the Differential Nonlinearity / Integral Nonlinearity (DNL/ INL) error are $\pm$0.5 / $\pm$2 LSB, respectively. The power consumption is 13㎽ at 10MS/s.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.6
• /
• pp.58-70
• /
• 1997

In this paper, an 8bit CMOS low power, high-speed current-mode folding and interpolation A/D converter is designed with te LG semicon $0.8\mu\textrm{m}$ N-well single-poly/double-metal CMOS process to be integrated into a portable image signal processing system such as a digital camcoder. For good linearity and low power consumption, folding amplifiers and for high speed performance of the A/D converter, analog circuitries including folding block, current-mode interpolation circuit and current comparator are designed as a differential-mode. The fabricated 8 bit A/D converter occupies the active chip area of TEX>$2.2mm \times 1.6mm$ and shows DNL of $\pm0.2LSB$, INL of <$\pm0.5LSB$, conversion rate of 40M samples/s, and the measured maximum power dissipation of 33.6mW at single +5V supply voltage.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
• /
• 2002.02a
• /
• pp.358-361
• /
• 2002

The millirneterwave high-T$_{c}$ superconducting(HTS) down-converter sub-system with the HTS/III-V integrated mixer as the central device is demonstrated first. The constituent components of HTS down-converter sub-system such as a single balanced type integrated mixer with rat-race coupler, a cavity type bandpass filter (26 GHz), and a HTS planar lowpass filter(1 GHz), semiconductor LNA and IF-power amplifier, a driving electronic module for A/D converter, and a Stirling type mini-cooler module were combined into an International stand- and rack of 19-inch. From the RF(-61 dBm, 26.5GHz)and LO signal(-1 dBm, 25.6 GHz), IF signal(0dBm, 0.9 GHz) agreed with simulated results is obtained.d.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.443-444
• /
• 2008

A double-balanced frequency up-converter using the Gilbert cell structure has been designed with the TSMC $0.18\;{\mu}m$ CMOS library. The frequency up-converter consists of a Mixer core and IF / LO balun. Frequency Up-converter exhibits a 3.4 dB conversion gain with a - 7.6 dBm $P_{1dB}$ for IF power of -10 dBm and LO power of 0 dBm inputs. It also exhibits 92.2 % modulation depth as a ASK modulator.

• Proceedings of the KIEE Conference
• /
• 1993.07b
• /
• pp.1206-1208
• /
• 1993

This paper is to study and realize a measuring device for complex dielectric constants. The device is consisted in order of interface unit, external RAM, programmable counter, D/A converter, measuring circuit, Sample & Hold circuit, A/D converter and related control circuits. Various excitation waves are digitalized and sent to the 4096 static RAM by personal computer. These data saved in the RAM are converted to analog excitation waves through D/A converter. The frequency of excitation wave is depend on the read-out speed of the RAM according to clock pulses. Such generated waves are applied to dielectrics under test and their responses are sampled and converted to digital data through A/D converter. The computer takes the digital data and calculates finally the complex dielectric constants. The frequencies for Measurement ranges from 0.04 Hz to 10 kHz.

• ETRI Journal
• /
• v.35 no.1
• /
• pp.109-119
• /
• 2013

Static testing of analog-to-digital (A/D) and digital-to-analog (D/A) converters becomes more difficult when they are embedded in a system on chip. Built-in self-test (BIST) reduces the need for external support for testing. This paper proposes a new static BIST structure for testing both A/D and D/A converters. By sharing test circuitry, the proposed BIST reduces the hardware overhead. Furthermore, test time can also be reduced using the simultaneous test strategy of the proposed BIST. The proposed method can be applied in various A/D and D/A converter resolutions and analog signal swing ranges. Simulation results are presented to validate the proposed method by showing how linearity errors are detected in different situations.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.27 no.1
• /
• pp.74-79
• /
• 2022

This paper proposes a DC-DC converter that satisfies a wide output voltage of 150 V-1000 V for the battery voltage of various electric vehicles and can be controlled in both directions for the demand resource of electric vehicles. The proposed converter is a two-stage structure in which an insulated converter and a non-isolated converter are combined and operates as constant current or constant power depending on the voltage of the connected battery. Experimental results from a 20 kW prototype are provided to validate the proposed charger, and a maximum efficiency of 97% is obtained.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.69-72
• /
• 2002

This paper proposed a new charge-shared switching MDAC for a pipelined A/D converter The proposed architecture accomplishes the same function of a conventional multiplying-digital-to-analog converter (MDAC). By adopting the proposed scheme, about 40% of the total capacitances could be reduced and the speed of the MDAC increases. The performance of the charge-shared switching MDAC has been Proved by HSPICE simulations.

• Progress in Superconductivity and Cryogenics
• /
• v.4 no.1
• /
• pp.8-12
• /
• 2002

Since the high performance analog-to-digital converter can be built with Rapid Single Flux Quantum (RSFQ) logic circuits the development of superconductive analog-to-digital converter has attracted a lot of interests as one of the most prospective area of the application of Josephson Junction technology. One of the main advantages in using Rapid Sng1e Flux Quantum logic in the analog-to-digital converter is the low voltage output from the Josephson junction switching, and hence the high resolution. To design an analog-digital converter, first we have used XIC tool to compose a circuit schematic, and then studied the operational principle of the circuit with WRSPICE tool. Through this process, we obtained the proper circuit diagram of an 1-bit analog-digital converter circuit. The optimized circuit was laid out as a mask drawing. Inductance values of the circuit layout were calculated with L-meter.