• 전자공학회논문지SC
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• 제47권2호
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• pp.35-42
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• 2010

본 논문은 A/D 변환기(Analog-to-Digital Converter) 회로에서 신호선의 터미네이션 조건이 crosstalk에 의해 왜곡되기 쉬운 특성을 가지며 동작 주파수가 높아짐에 따라 이에 대한 주의가 더욱 요구된다. 그중에서도 아날로그 신호인 입력 신호와 레퍼런스 전압 신호는 crosstalk에 의해 왜곡되기 쉬운 아날로그 신호이면서, A/D 변환 전체의 동작 성능을 좌우하는 신호들이다. 이 두 신호들은 각각의 회로 구성에 따라 독특한 터미네이션 조건을 가지므로 본 논문에서는 주파수 영역에서 임피던스 불일치 조건을 고려한 crosstalk를 모델링하고 해당 터미네이션 조건이 crosstalk에 미치는 영향을 확인한다. 먼저, A/D 변환기 회로에서 두 신호의 회로 구성을 파악한 후 near-end와 far-end에서 임피던스 불일치를 고려한 crosstalk 모델을 유도한다. 유도한 crosstalk 모델을 이용하여 입력 신호의 near-end와 터미네이션 임피던스 불일치와 레퍼런스 전압 신호의 far-end 커패시턴스 터미네이션이 crosstalk에 미치는 영향을 예측하고, 실험을 통해 예측 결과를 확인한다. 신호선으로는 가장 널리 사용되는 microstrip 구조를 사용하였으며 skin effect에 의한 손실 증가를 반영하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.263-266
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• 1999

In this work, a A/D converter is implemented to obtain 8bit resolution at a conversion rate of 10MS/s for video applications. This architecture is proposed using the Pipelined architecture for high speed conversion rate and the Successive - Approximation architecture for low power consumption, and consists of two identical stages that consist of sample/hold circuit, low power comparator, voltage reference circuit and MDAC of binary weighted capacitor array. Proposed A/D converter is designed using 0.25${\mu}{\textrm}{m}$ CMOS technology The SNR is 80㏈ at a sampling rate of 10MHz with 1.95MHz sine input signal. When an 8bit 10MS/s A/D converter is simulated, the Differential Nonlinearity / Integral Nonlinearity (DNL/ INL) error are $\pm$0.5 / $\pm$2 LSB, respectively. The power consumption is 13㎽ at 10MS/s.

• 전자공학회논문지C
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• 제34C권6호
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• pp.58-70
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• 1997

In this paper, an 8bit CMOS low power, high-speed current-mode folding and interpolation A/D converter is designed with te LG semicon $0.8\mu\textrm{m}$ N-well single-poly/double-metal CMOS process to be integrated into a portable image signal processing system such as a digital camcoder. For good linearity and low power consumption, folding amplifiers and for high speed performance of the A/D converter, analog circuitries including folding block, current-mode interpolation circuit and current comparator are designed as a differential-mode. The fabricated 8 bit A/D converter occupies the active chip area of TEX>$2.2mm \times 1.6mm$ and shows DNL of $\pm0.2LSB$, INL of <$\pm0.5LSB$, conversion rate of 40M samples/s, and the measured maximum power dissipation of 33.6mW at single +5V supply voltage.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2002년도 학술대회 논문집
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• pp.358-361
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• 2002

The millirneterwave high-T$_{c}$ superconducting(HTS) down-converter sub-system with the HTS/III-V integrated mixer as the central device is demonstrated first. The constituent components of HTS down-converter sub-system such as a single balanced type integrated mixer with rat-race coupler, a cavity type bandpass filter (26 GHz), and a HTS planar lowpass filter(1 GHz), semiconductor LNA and IF-power amplifier, a driving electronic module for A/D converter, and a Stirling type mini-cooler module were combined into an International stand- and rack of 19-inch. From the RF(-61 dBm, 26.5GHz)and LO signal(-1 dBm, 25.6 GHz), IF signal(0dBm, 0.9 GHz) agreed with simulated results is obtained.d.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.443-444
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• 2008

A double-balanced frequency up-converter using the Gilbert cell structure has been designed with the TSMC $0.18\;{\mu}m$ CMOS library. The frequency up-converter consists of a Mixer core and IF / LO balun. Frequency Up-converter exhibits a 3.4 dB conversion gain with a - 7.6 dBm $P_{1dB}$ for IF power of -10 dBm and LO power of 0 dBm inputs. It also exhibits 92.2 % modulation depth as a ASK modulator.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.1206-1208
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• 1993

This paper is to study and realize a measuring device for complex dielectric constants. The device is consisted in order of interface unit, external RAM, programmable counter, D/A converter, measuring circuit, Sample & Hold circuit, A/D converter and related control circuits. Various excitation waves are digitalized and sent to the 4096 static RAM by personal computer. These data saved in the RAM are converted to analog excitation waves through D/A converter. The frequency of excitation wave is depend on the read-out speed of the RAM according to clock pulses. Such generated waves are applied to dielectrics under test and their responses are sampled and converted to digital data through A/D converter. The computer takes the digital data and calculates finally the complex dielectric constants. The frequencies for Measurement ranges from 0.04 Hz to 10 kHz.

• ETRI Journal
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• 제35권1호
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• pp.109-119
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• 2013

Static testing of analog-to-digital (A/D) and digital-to-analog (D/A) converters becomes more difficult when they are embedded in a system on chip. Built-in self-test (BIST) reduces the need for external support for testing. This paper proposes a new static BIST structure for testing both A/D and D/A converters. By sharing test circuitry, the proposed BIST reduces the hardware overhead. Furthermore, test time can also be reduced using the simultaneous test strategy of the proposed BIST. The proposed method can be applied in various A/D and D/A converter resolutions and analog signal swing ranges. Simulation results are presented to validate the proposed method by showing how linearity errors are detected in different situations.

• 전력전자학회논문지
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• 제27권1호
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• pp.74-79
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• 2022

This paper proposes a DC-DC converter that satisfies a wide output voltage of 150 V-1000 V for the battery voltage of various electric vehicles and can be controlled in both directions for the demand resource of electric vehicles. The proposed converter is a two-stage structure in which an insulated converter and a non-isolated converter are combined and operates as constant current or constant power depending on the voltage of the connected battery. Experimental results from a 20 kW prototype are provided to validate the proposed charger, and a maximum efficiency of 97% is obtained.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.69-72
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• 2002

This paper proposed a new charge-shared switching MDAC for a pipelined A/D converter The proposed architecture accomplishes the same function of a conventional multiplying-digital-to-analog converter (MDAC). By adopting the proposed scheme, about 40% of the total capacitances could be reduced and the speed of the MDAC increases. The performance of the charge-shared switching MDAC has been Proved by HSPICE simulations.

• 한국초전도ㆍ저온공학회논문지
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• 제4권1호
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• pp.8-12
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• 2002

Since the high performance analog-to-digital converter can be built with Rapid Single Flux Quantum (RSFQ) logic circuits the development of superconductive analog-to-digital converter has attracted a lot of interests as one of the most prospective area of the application of Josephson Junction technology. One of the main advantages in using Rapid Sng1e Flux Quantum logic in the analog-to-digital converter is the low voltage output from the Josephson junction switching, and hence the high resolution. To design an analog-digital converter, first we have used XIC tool to compose a circuit schematic, and then studied the operational principle of the circuit with WRSPICE tool. Through this process, we obtained the proper circuit diagram of an 1-bit analog-digital converter circuit. The optimized circuit was laid out as a mask drawing. Inductance values of the circuit layout were calculated with L-meter.