• Journal of Communications and Networks
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• v.10 no.3
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• pp.253-257
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• 2008

In this paper, the performance of generic orthogonal space-time block codes (OSTBCs) introduced by Alamouti [2], Tarokh [3], and Su and Xia [11] is analyzed. We first define one-dimensional component symbol error function (ODSEF) from the exact expression of the pairwise error probability of an OSTBC. Utilizing the ODSEF and the bit error probability (BEP) expression for quadrature amplitude modulation (QAM) introduced by Cho and Yoon [9], the exact closed-form expressions for the BEP of linear OSTBCs with QAM in quasi-static Rayleigh fading channel are derived. We also derive the exact closed-form of the BEP for some OSTBCs which have at least one message symbol transmitted with unequal power via all transmit antennas.

• Journal of Communications and Networks
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• v.9 no.2
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• pp.136-140
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• 2007

In this paper, an adaptive minimum transmit power modulation scheme under constant data rate and fixed bit error rate (BER) for the multiple-input multiple-output (MIMO) system is proposed. It adjusts the modulation order and allocates the transmit power to each spatial sub-channel when meeting the user's requirements at the cost of minimum transmission power. Compared to the other algorithm, it can obtain good performance with lower computational complexity and can be applied to the wireless communication system. Computer simulation results present the efficiency of the proposed scheme. And its performance under different channel condition has been compared with the other algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9A
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• pp.1383-1391
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• 1999

This paper presents a rate control method that minimizes global distortion under given target bit rates for video communication. This method makes the quality of reconstructed images better than that of the conventional ones based on R-D model at the same bit rates. Given a set of quantizers, a sequence of macroblocks to be quantized selects the optimal quantizer for each macroblock so that the total cost measure is minimized and the finite buffer is never in overflow. To solve this problem we provide a heuristic algorithm based on Lagrangian optimization using an operational rate-distortion framework and a quantization method follows H.263recommendation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1174-1181
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• 2005

The exact bit error rate(BER) calculation of an UWB-TH PPM multiple access communication system, which is known to be suitable for the fast transmission of massive information data, is introduced. The statistic feature of the multiple access intereference (MAI) of the system is precisely modeled by the characteristic function technique. The concrete expression for the MAI allows the exact expression for BER to be derived. In addition, we propose the approximate expression for the BER which reveals superior accuracy to the expression from the previous Gaussian approximation of the MAI. The validity of the proposed expressions is confirmed from the comparison of proposed results with the results from Monte-Carlo simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.9
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• pp.781-786
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• 2013

Multiplexing information over parallel data channels based on RF MIMO concept is possible to achieve considerable data rates over large transmission ranges with just a single transmitting element. Visual multiplexing MIMO techniques will send independent streams of bits using the multiple elements of the light transmitter array and recording over a group of camera pixels can further enhance the data rates. The proposed system is a combination of the reliance on computer vision algorithms for tracking and OOK cell frame modulation. LED array are controlled to transmit message in the form of digital information using ON-OFF signaling with ON-OFF pulses (ON = bit 1, OFF = bit 0). A camera captures image frames of the array which are then individually processed and sequentially decoded to retrieve data. To demodulated data transmission, a motion tracking algorithm is implemented in OpenCV (Open source Computer Vision library) to classify the transmission pattern. One of the most advantages of proposed architecture is Computer Vision (CV) based image analysis techniques which can be used to spatially separate signals and remove interferences from ambient light. It will be the future challenges and opportunities for mobile communication networking research.

• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.9A
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• pp.1574-1582
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• 2001

본 논문에서는 무선 ATM 망에서 VBR 트래픽에 대한 동적인 대역할당 기법을 제안하였다. 제안된 기법에서는 동적 파라미터를 전송하기 위하여 인 밴드 방식을 사용하였으며, 버퍼의 길이와 변이를 고려하여 이동국에서 2 state bit를 기지국에서 전송하도록 하였다. 기지국에서 수신된 비트의 상태에 따라서 이동국에 데이터 슬롯을 할당한다. 제안한 알고리즘은 VBR 트래픽의 QoS를 보장하고, 시스템의 효율을 높일 수 있도록 하였고, 컴퓨터 시뮬레이션을 통하여 제안된 알고리즘의 성능을 평가하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.9A
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• pp.1422-1430
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• 2000

S(Synchronous)-CDMA is a new cable modem technology applicable to the upstream channel for high speed multimedia communication using CATV networks. In this paper we analyze the transmitting and receiving process of S-CDMA scheme based on Terayon patent and derive bit error probability of S-CDMA and TDMA scheme in the $\varepsilon$-mixture impulse noise model which appropriately reflects impulse noise characteristics of upstream channel by using various parameters. This analysis results are a good match with the simulation results. We also compare Eb/No gain performance of S-CDMA with TDMA in 16, 32, 64, QAM.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.8 no.4
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• pp.310-318
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• 2015

In this paper, dual-port eFuse OTP (one-time programmable) memory cells with smaller cell sizes are used, a single VREF (reference voltage) is used in the designed eFuse OTP IP (intellectual property), and a BL (bit-line) sensing circuit using a S/A (sense amplifier) based D F/F is proposed. With this proposed sensing technique, the read current can be reduced to 3.887mA from 6.399mA. In addition, the sensing resistances of a programmed eFuse cell in the program-verify-read and read mode are also reduced to $9k{\Omega}$ and $5k{\Omega}$ due to the analog sensing. The layout size of the designed 32-bit eFuse OTP memory is $187.845{\mu}m{\times}113.180{\mu}m$ ($=0.0213{\mu}m2$), which is confirmed to be a small-area implementation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.788-791
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• 2010

We design 64-bit ROM IP for RFID tag chips using printed CMOS non-volatile memory IP design technology for a printed CMOS process. The proposed 64-bit ROM circuit is using ETRI's $0.8{\mu}m$ CMOS porocess, and is expected to reduce process complexity and cost of RFID tag chips compared to that using a conventional silicon fabrication based on a complex lithography process because the poly layer in a gate terminal is using printing technology of imprint process. And a BL precharge circuit and a BL sense amplifier is not required for the designed cell circuit since it is composed of a transmission gate instead of an NMOS transistor of the conventional ROM circuit. Therefore an output datum is only driven by a DOUT buffer circuit. The Operation current and layout area of the designed ROM of 64 bits with an array of 8 rows and 8 columns using $0.8{\mu}m$ ROM process is $9.86{\mu}A$ and $379.6{\times}418.7{\mu}m^2$.