• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.4
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• pp.31-37
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• 2010

In this paper, highly efficient dual-band class-F power amplifiers(PAs) for cellular and WLAN bands are suggested and implemented. For the first step, single-band class-F amplifiers at 840MHz, 2.4GHz are designed using commercial E-pHEMT FETs. The performance of two single band PAs are as much as 81.2% of efficiency with the output power of 24.4dBm with 840MHz PA and 93.5% of efficiency with 22.4dBm from the 2.4GHz. For the dual-band class-F PA, the harmonic controlling circuit with ideal SPDT switch was suggested. The length of transmission line is variable by a SPDT switch. As a results, the operation in 840MHz showed the peak efficiency of 60.5% with 23.5dBm, while in 2.4GHz mode the efficiency was 50.9% with the output power of 19.62dBm. Besides, it is shown that the harmonic controller of class-F above 2Ghz could be implemented on the low cost FR-4 substrate.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.7
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• pp.704-709
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• 2007

In this paper, a CPW band-pass filter with a rejection band is proposed for UWB(Ultra-Wideband) communication systems. The proposed filter has a band-pass characteristic of wide-band by inserting only a slot in $50{\Omega}$ transmission line. To obtain the band-rejection function at WLAN frequency band($5.15{\sim}5.725GHz$), the designed filter is combined with folded slot resonators on the ground plane of the CPW structure. The fabricated CPW band-pass filter shows a compact size of $15.35{\times}13.60mm$, a wide passband of 2.8 GHz to 9.8 GHz and the narrow stop-band of 5.15 GHz to 5.71 GHz for 3-dB bandwidth. Also, the measured group delay is less than 400 psec throughout the operation frequency band except the rejection band.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.670-680
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• 2010

A low power single-chip CMOS receiver for 60 GHz mobile application are proposed in this paper. The single-chip receiver consists of a 4-stage current re-use LNA with under 4 dB NF, Cgs compensating resistive mixer with -9.4 dB conversion gain, Ka-band low phase noise VCO with -113 dBc/Hz phase noise at 1 MHz offset from 26.89 GHz, high-suppression frequency doubler with -0.45 dB conversion gain, and 2-stage current re-use drive amplifier. The size of the fabricated receiver using a standard 0.13 ${\mu}m$ CMOS technology is 2.67 mm$\times$0.75 mm including probing pads. An RF bandwidth is 6.2 GHz, from 55 to 61.2 GHz and an LO tuning range is 7.14 GHz, from 48.45 GHz to 55.59 GHz. The If bandwidth is 5.25 GHz(4.75~10 GHz) The conversion gain and input P1 dB are -9.5 dB and -12.5 dBm, respectively, at RF frequency of 59 GHz. The proposed single-chip receiver describes very good noise performances and linearity with very low DC power consumption of only 21.9 mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.60-67
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• 2008

A low-power 2.4GHz fractional-N frequency synthesizer has been designed for 2.4GHz ISM band applications such as Bluetooth, Zigbee, and WLAN. To achieve low-power characteristic, the design has been focused on the power optimization of power-hungry blocks such as VCO, prescaler, and ${\Sigma}-{\Delta}$ modulator. An NP-core type VCO is adopted to optimize both phase noise and power consumption. Dynamic D-F/Fs with no static DC current are employed in designing the low-power prescaler circuit. The ${\Sigma}-{\Delta}$ modulator is designed using a modulus mapping circuit for reducing hardware complexity and power consumption. The designed frequency synthesizer which was fabricated using a $0.18{\mu}m$ CMOS process consumes 7.9mA from a single 1.8V supply voltage. The experimental results show that a phase noise of -118dBc/Hz at 1MHz offset, the reference spur of -70dBc at 25MHz offset, and the channel switching time of $15{\mu}s$ over 25MHz transition have been achieved. The designed chip occupies an area of $1.16mm^2$ including pads where the core area is only $0.64mm^2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.3
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• pp.300-305
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• 2012

In this paper, a miniaturized bow-tie monopole UWB antenna with band rejection characteristic is proposed. To miniaturize the proposed antenna, a perfect magnetic wall(PMW) condition is applied to primitive bow-tie monopole antenna. An uneven ground patch, a tapered feeding structure and a edge-chopped main patch are adapted for impedance matching. A quater-lambda slot resonator is inserted at main patch to prevent interference in UWB band from another band. The proposed antenna is fabricated on Taconic RF60-A substrate with relative permittivity of 6.15. The size of the proposed antenna is $30.0{\times}39.7mm^2$, which is only 45 % of the conventional bow-tie monopole antenna. The proposed antenna covers full UWB band with return losses less than -10 dB and has band stop characteristic in 5 GHz WLAN band. The maximum gains are within -1.0~5.0 dBi, the group delay variations are within 1.0 ns and the radiation patterns show directivity characteristics in x-y plane.