• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.8
• /
• pp.117-124
• /
• 2009

This paper describes a 3 to 5 GHz frequency synthesizer for MB-OFDM (Multi-Band OFDM) UWB (Ultra- Wideband) application using 0.13 ${\mu}m$ CMOS process. The frequency synthesizer operates in the band group 1 whose center frequencies are 3432 MHz 3960 MHz, and 4488 MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and LO Mixer architecture are also presented in this paper. A new mixed coarse tuning scheme that utilizes the MIM capacitance, the varactor arrays, and the DAC is proposed to expand the VCO tuning range. The frequency synthesizer can also provide the clock for the ADC in baseband modem. So, the PLL for the ADC in the baseband modem can be removed with this frequency synthesizer. The single PLL and two SSB-mixers consume 60 mW from a 1.2 sV supply. The VCO tuning range is 1.2 GHz. The simulated phase noise of the VCO is -112 dBc/Hz at 1 MHz offset. The die area is 2 ${\times}$ 2mm$^2$.

• Journal of electromagnetic engineering and science
• /
• v.6 no.1
• /
• pp.18-23
• /
• 2006

In this paper, we demonstrate a fully integrated X-band image rejection down converter, which was developed using InGaP/GaAs HBT MMIC technology, consists of two single-balanced mixers, a differential buffer amplifier, a differential YCO, an LO quadratue generator, a three-stage polyphase filter, and a differential intermediate frequency(IF) amplifier. The X-band image rejection downconverter yields an image rejection ratio of over 25 dB, a conversion gain of over 2.5 dB, and an output-referred 1-dB compression power$(P_{1dB,OUT})$ of - 10 dBm. This downconverter achieves broadband image rejection characteristics over a frequency range of 1.1 GHz with a current consumption of 60 mA from a 3-V supply.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.42 no.5 s.335
• /
• pp.55-60
• /
• 2005

A V-band MIMIC quadruple subharmonic mixer is reported in this paper. The cascode harmonic generator is proposed for a high conversion gain. The proposed cascode harmonic generator is shown with a 4-th harmonic output characteristic that represents an average of 2.9 dB and a maximum of 4 dB higher than the conventional multiplier. The measured result of the subharmonic mixer has a conversion gain of 3_4 dB which a good conversion gain at a LO power of 13 dBm. Isolations of LO-to-IF and LO-to-RF were obtained -53.6 dB and -46.2 dB, respectively. The conversion gain of the subharmonic mixer in this study has a higher conversion gain compared with some other reports in millimeter-wave range.

• Journal of Advanced Marine Engineering and Technology
• /
• v.37 no.1
• /
• pp.99-104
• /
• 2013

In this paper, we developed a fully integrated downconverter MMIC (monolithic microwave integrated circuit) including Lange coupler and output active balun for millimeter wave applications. Concretely, ${\lambda}$/4 transmission line was added to Lange coupler for size reduction of RF/LO input, and mixed RF/LO signals were applied to gate of the FET of mixer. Active balun was used at output port for a coupling of out-of-phase IF output signals. According to measured results, the proposed downconverter MMIC showed good RF performances. For example, the downconverter MMIC showed an LO leakage power of -25 dBc at IF output port, and a RF-LO isolation of 18 dB. Therefore, off-chip components such as LO rejection filters were not required for a normal operation of the proposed downconverter MMIC. The proposed downconverter MMIC showed a conversion gain of 10.3 dB at RF frequency of 63 GHz. The size of the downconverter MMIC including all active and passive components was $2.2{\times}1.4mm^2$.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
• /
• 2001.11a
• /
• pp.213-217
• /
• 2001

본 논문에서는 CPW 구조를 이용하여 60 GHz 무선 시스템 응용을 위한 V-band용 하향 주파수 혼합기를 설계 및 제작하였다. 하향 주파수 혼합기의 설계 및 제작에 있어서 GaAs PHEMT(Pseudomorphic high electron mobility transistor)를 기반으로 하였으며, 회로설계를 위해 coplanar waveguide(CPW) 라이브러리를 구축하여 이용하였다. 제작된 하향 주파수 혼합기의 변환이득은 국부발진주파수(LO) 입력이 8 dBm일 때 -8.5 dB의 최대 변환이득 특성을 얻었으며 Pl dB는 -3.3 dBm을 얻었다. 제작된 회로의 칩 크기는 1.6$\times$l.6 $\textrm{mm}^2$ 이다.