• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.145-148
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• 2000

A 16bit asynchronous multiplier has been designed using micropipelind structure with 2 phase and data bundling. And 4-radix modified Booth algorithm, CPlatch(Cature-Pass latch) and modified 4-2 counters have adopted in this design. It is implemented in 0.65$\mu\textrm{m}$ double-poly/double-metal CMOS technology by using 12,074 transistors with core size of 1.4${\times}$1.8$\textrm{mm}^2$. And our design results in a computation rate 55MHz a supply voltage of 3.3V.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2003년도 봄 학술발표논문집 Vol.30 No.1 (C)
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• pp.581-583
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• 2003

현재 인터넷에서는 사용자의 급격만 증가로 인해 고성능의 라우터를 요구하고 있고 주소부족으로 IPv4에서 IPv6로 변화를 하고 있다. IPv4처럼 IPv6에서도 Address Lookup이 병목이 될 것이며 IPv4와는 달리 IPv6는 128bit의 주소 길이를 가지고 있어 이에 맞는 라우터 구조와 Address Lookup 알고리즘이 필요하다. 본 논문에서는 IPv6주소 128bit 중 외부에서 할당받는 64bit를 3단계로 나누는 계층적 네트워크 구성과 각 단계에 적합한 라우팅 테이블 구조와 Address Lookup 알고리즘에 대해 연구하였고 펜티엄 III 866MHz의 프로세서에서 알고리즘의 검색 시간을 측정해 각 단계에 맞는 라우팅 테이블 구조를 제안하였다.

• 전기학회논문지
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• 제57권6호
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• pp.1081-1086
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• 2008

This paper presents the $3^{rd}$ 4bit sigma delta modulator with the block and timing diagrams of DWA(Data Weighted Averaging) to optimize a operating time. In the modulator, the proposed DWA structure has a stable operation and timing margin so as to remove three latches and another clock. Because the modulator with proposed DWA structure improve timing margin about 23%. It can increase sampling frequency up to 244MHz. Through the MATLAB modeling, the optimized coefficients are obtained to design the modulator. The fully differential SC integrators, DAC, switch, quantizer, and DWA are designed by considering the nonideal characteristics. The designed $3^{rd}$ order 4bit modulator has a power consumption of 40mW and SNR(signal to noise ratio) of 77.2dB under 1.2V supply and 64MHz sampling frequency.

• 디지털산업정보학회논문지
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• 제4권4호
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• pp.9-19
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• 2008

In this paper, it is studied anti-collision algorithm based on the transmission protocol for RFID baseband system of the lSO/IEC 18000-6 Type-C regulation and designed the baseband part of RFID reader system using FPGA. To compensate this weak point of the slot random aloha algorithm which must have a long time to be dumped before deciding an appropriate slot size according to the number of surrounding tag, we suggested how to apply Bit By Bit algorithm to be able to recognize the tag when the tag is clashing. The design of the baseband part in the RFID reader system is accomplish by use of the ISE9.1i and I made an experiment on it targeting Spartan2. Construction verification is measured each block through Logic Analyzer and I can verify it has no error. I also compared and analyzed the performance between proposed algorithm and past algorithm and verified the improvement of performance.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅳ
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• pp.2056-2059
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• 2003

The rate control is very important to solve the difficulties arising from bit-rate on transmission through channel and to improve video quality. It is very important to point out that the amount of output bit obtained the encoding process using rate controller brings many problems on the transmission of channels and furthermore output bitstream decoded affects directly on the visual quality of displayed subject. In this paper, the effective rate control algorithm by rate-distortion modeling using MPEG-4 encoder is proposed. The proposed rate control has applied different weighting by VOP prediction type and even in the same VOP prediction type, the predicted reference allocates more bit. Through these bit allocation the minimization of distortion can be achieved preventing propagation of quantization error The amount of saved bitstream obtained by the proposed algorithm in this thesis is allocated to I-VOP using region of interest(ROI) selective enhancement on the next GOV encoding process and this process brought the improvement of visual quality.

• 한국항행학회논문지
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• 제11권4호
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• pp.388-393
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• 2007

변환부호화기(Transform coders)를 설계함에 있어서 비트 할당(Bit allocation)은 중요한 설계 요인 중의 하나이다. 본 논문에서는 고해상(high-resolution) 이론에 의한 수식들을 바탕으로 각 계수 양자화기들의 비트율을 정수값으로 할당해주는 최적의 알고리즘인 최대 탐욕 알고리즘과 최소 탐욕 알고리즘을 제안하였다. 특히, 제안된 최대 탐욕 알고리즘과 최소 탐욕 알고리즘에서 쌍대성(duality) 성질을 확인할 수 있었다.

• ETRI Journal
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• 제24권4호
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• pp.280-289
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• 2002

In this work, we present a novel approach to the bit allocation problem that aims to minimize overall distortion subject to a bit rate constraint. The optimal solution can be found by the Lagrangian method with dynamic programming. However, the optimal bit allocation for block-based interframe coding is practically unattainable because of the interframe dependency of macroblocks caused by motion compensation. To reduce the computational burden while maintaining a result close to the optimum, i.e., near optimum, we propose an alternative method. First, we present a partitioned form of the bit allocation problem: a "frame-level problem" and "one-frame macroblock-level problems." We show that the solution to this new form is also the solution to the conventional bit allocation problem. Further, we propose a bit allocation algorithm using a "two-phase optimization technique" with an interframe dependency model and a rate-distortion model.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제14권2호
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• pp.724-737
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• 2020

Corrected Block TEA(or XXTEA) is a block cipher designed to correct security weakness in the original block TEA in 1998. In this paper, XXTEA cipher hardware which can encrypt or decrypt between 64-bit and 256-bit messages using 128-bit master key is implemented. Minimum message block size is 64-bit wide and maximal message block size is 256-bit wide. The designed XXTEA can encrypt and decrypt variable-length message blocks which are some arbitrary multiple of 32 bits in message block sizes. XXTEA core of this paper is described using Verilog-HDL and downloaded on Vertex4. The operation frequency is 177MHz. The maximum throughput for 64-bit message blocks is 174Mbps and that of 256-bit message blocks is 467Mbps. The cryptographic IP of this paper is applicable as security module of the mobile areas such as smart card, internet banking, e-commerce and IoT.

• 전자공학회논문지B
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• 제33B권4호
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• pp.209-216
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• 1996

In this paper, we propose a learning method of multi-layer perceptrons (MLPs) with 8-bit data precision. The suggested method uses the cross-entropy cost function to remove the slope term of error signal in output layer. To decrease the possibility of overflows, we use 16-bit weighted sum results into the 8-bit data with appropriate range. In the forwared propagation, the range for bit-conversion is determined using the saturation property of sigmoid function. In the backwared propagation, the range for bit-conversion is derived using the probability density function of back-propagated signal. In a simulation study to classify hadwritten digits in the CEDAR database, our method shows similar generalization performance to the error back-propagation learning with 16-bit precision.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제17권4호
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• pp.1296-1309
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• 2023

In this paper, based on the soft cancellation (SCAN) bit-flipping (SCAN-BF) algorithm, a generalized SCAN bit-flipping (GSCAN-BF-Ω) decoding algorithm is carried out, where Ω represents the number of bits flipped or corrected at the same time. GSCAN-BF-Ω algorithm corrects the prior information of the code bits and flips the prior information of the unreliable information bits simultaneously to improve the block error rate (BLER) performance. Then, a joint threshold scheme for the GSCAN-BF-2 decoding algorithm is proposed to reduce the average decoding complexity by considering both the bit channel quality and the reliability of the coded bits. Simulation results show that the GSCAN-BF-Ω decoding algorithm reduces the average decoding latency while getting performance gains compared to the common multiple SCAN bit-flipping decoding algorithm. And the GSCAN-BF-2 decoding algorithm with the joint threshold reduces the average decoding latency further by approximately 50% with only a slight performance loss compared to the GSCAN-BF-2 decoding algorithm.