• Title/Summary/Keyword: 4-Bit Pattern

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A Method for Optimal Binarization using Bit-plane Pattern (비트평면 패턴을 이용한 최적 이진화 방법)

  • Kim, Ha-Sik;Kim, Kang;Cho, Kyung-Sik;Jeon, Jong-Sik
    • Journal of the Korea Society of Computer and Information
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    • v.6 no.4
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    • pp.1-5
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    • 2001
  • A new approach for determining global threshold value for image binarization is proposed in this paper. In the proposed algorithm, bit-plane information which involve the shapes of original image is used for dividing image into two parts object and background, and then compared each average values. Optimal threshold value are selected in center of two averages. Proposed method is relatively simple but robust and achieved good results in continuous tone images and document image.

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A Study on the Minimal Test Pattern of the RAM (RAM의 최소 테스트 패턴에 관한 연구)

  • 김철운;정우성;김태성
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1996.11a
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    • pp.23-25
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    • 1996
  • In this paper aims at studying the minimal test pattem of the RAM. This also propose a scheme of testing faults from the new fault model using the LLB. The length of test patterns are 6N(1-wsf), 9.5N(2-wsf), 7N(3-wsfl, 3N(4-wsf) operations in N-bit RAM. This test techniques can write into memory cell the number of write operations is reduced and then much testing time is saved. A test set which detects all positive-negative static t-ws faults for t=0, 1, 2, 3, 4 and detects all pattern sensitive fault in memory array. A new fault model, which encompasses the existing fault model Is proposed.

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A Study on the Test Strategy Based on SSA Technique for the Digital Circuit Boards in Production Line (SSA 기법에 기반한 생산조립라인의 디지털 부품 실장 PCB의 검사전략에 대한 연구)

  • Jung Yong-Chae;Ko Yun-Seok
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.54 no.4
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    • pp.243-250
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    • 2005
  • Test methodology is diversity by devices and the number of test pattern is tremendous because the digital circuit includes TTL and CMOS family ICs as well as high density devices such as ROM and RAM. Accordingly, the quick and effective test strategy is required to enhance the test productivity. This paper proposes the test strategy which is able to be applied efficiently to the diversity devices on the digital circuit board by analyzing the structure and characteristic of the digital device. Especially, this test strategy detects the faulted digital device or the faulted digital circuit on the digital board using SSA(Serial Signature Analysis) technique based on the polynomial division theory The SSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Register) representing the characteristic equation. Also, the method to obtain the optimal signature analysis circuit is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

Modulation Code for Removing Error Patterns on 4-Level NAND Flash Memory (4-레벨 낸드 플래시 메모리에서 오류 발생 패턴 제거 변조 부호)

  • Park, Dong-Hyuk;Lee, Jae-Jin;Yang, Gi-Ju
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.12C
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    • pp.965-970
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    • 2010
  • In the NAND flash memory storing two bits per cell, data is discriminated among four levels of electrical charges. We refer to these four levels as E, P1, P2, and P3 from the low voltage. In the statistics, many errors occur when E and P3 are stored at the next cells. Therefore, we propose a coding scheme for avoiding E-P3 or P3-E data patterns. We investigate two modulation codes for 9/10 code (9 bit input and 5 symbol codeword) and 11/12 code (11 bit input and 6 symbol codeword).

An Anti-Collision Algorithm with 4-Slot in RFID Systems (RFID 시스템에서 4 슬롯을 이용한 충돌방지 알고리즘)

  • Kim, Yong-Hwan;Kim, Sung-Soo;Ryoo, Myung-Chun;Park, Joon-Ho;Chung, Kyung-Ho
    • Journal of the Korea Society of Computer and Information
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    • v.19 no.12
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    • pp.111-121
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    • 2014
  • In this paper, we propose tree-based hybrid query tree architecture utilizing time slot. 4-Bit Pattern Slot Allocation(4-SL) has a 8-ary tree structure and when tag ID responses according to query of the reader, it applies a digital coding method, the Manchester code, in order to extract the location and the number of collided bits. Also, this algorithm can recognize multiple Tags by single query using 4 fixed time slots. The architecture allows the reader to identify 8 tags at the same time by responding 4 time slots utilizing the first bit($[prefix+1]^{th}$, F ${\in}$ {'0' or '1'}) and bit pattern from second ~ third bits($[prefix+2]^{th}{\sim}[prefix+3]^{th}$, $B_2{\in}$ {"00" or "11"}, $B_1{\in}$ {"01" or "10"}) in tag ID. we analyze worst case of the number of query nodes(prefix) in algorithm to extract delay time for recognizing multiple tags. The identification delay time of the proposed algorithm was based on the number of query-responses and query bits, and was calculated by each algorithm.

OCR Application By a FPGA Programming AND/OR Neural Network

  • Park, Pyong-Sik;Kim, Gwan
    • 제어로봇시스템학회:학술대회논문집
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    • 2002.10a
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    • pp.42.4-42
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    • 2002
  • With the research of simplified neural networks, we propose an AND/OR neural network; a kind of brief, fast network Then, we present an OCR solution that equip the network in one-chip FPGA and design it by using HDL. We selected the representative hexadecimal character as the recognition feature class and used a Feature Vector Recognition Method in the statistic pattern recognition. The result feature vector was encoded into a 7 bit array and inputted into the AND/OR network to finish learning.

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2D Pattern Development of Tight-fitting Bodysuit from 3D Body Scan Data for Comfortable Pressure Sensation (인체의 3차원 스캔 데이터를 이용한 밀착 바디 슈트 개발)

  • Jeong, Yeon-Hee
    • Korean Journal of Human Ecology
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    • v.15 no.3
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    • pp.481-490
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    • 2006
  • Adjusting pressure level in the construction of athletes' tight-fitting garments by reducing the elastic knit pattern is a challenging subject, which influences the performance of the wearer directly. Therefore, in this study, relationship between the reduction rates of the basic pattern obtained from 3D human scan data and resultant clothing pressure was explored to improve the fit and pressure exerted by clothing. 3D scan data were obtained using Cyberware and they were transformed into a flat pattern using software based on Runge-Kutta method. Reduction rate was examined by subjective wear test as well as objective pressure measurement. As a result, difference in the length between the original 3D body scan data and the 2D tight-fitting pattern was 0.02$\sim$0.50cm (0.05$\sim$1.06%), which was within the range of tolerable limits in making clothes. Among the five garments, the 3T-pattern was superior in terms of subjective sensation and fit. The pressure of the 3T pattern was 2$\sim$4 gf/cm2 at five locations on the body, which is almost the same or a bit higher than that of Z-pattern. In the case of tight-fitting overall garment, the reduction rate of the pattern in the wale direction is more critical to the subjective sensation than the course direction. It is recommended that the reduction grading rules of course direction should be larger than that of Ziegert for a better fit of tight-fitting garments. In the case of wale direction, however, reduction grading rule should be kept the same as suggested earlier by Ziegert (1988).

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Eye Pattern Characteristic Based Active Stabilization Method for Direct Delection Receiver in Differential Phase Shift Key System (차동 위상 변조 전송 시스템에서 수신 신호 눈열림 특성을 이용한 직접 검출 수신단 최적화 및 안정화 제어 연구)

  • Jang, Youn-Seon;Park, Heuk;Kim, Kwang-Joon
    • Korean Journal of Optics and Photonics
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    • v.16 no.4
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    • pp.313-318
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    • 2005
  • We propose an active stabilization method for the receiver of NRZ-DPSK transmission. The 1-bit delayed Mach-Zehlder interferometer is thermally controlled to maintain the largest DC component power ratio between the constructive and destructive output ports, for the optimum transmission condition. This method is very cost effective since no additional components are required. Experimental results show that the proposed scheme guarantees error free performance even when there was ~ 1 GHz optical carrier frequency fluctuation in 10 Gbps transmission.

Performance analysis of SNR and BER for radiation pattern reconfigurable antenna (인체 부착용 방사패턴 재구성 안테나의 SNR 및 BER 성능 분석)

  • Lee, Chang Min;Jung, Chang Won
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.16 no.6
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    • pp.4125-4130
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    • 2015
  • This paper presents the communication performance for the radiation pattern reconfigurable antenna in the wearable device measuring bio signal (temperature, blood pressure, pulse etc.) of human body. The operational frequency is 2.4 - 2.5 GHz, which covers Bluetooth communication bandwidth. The maximum gain of the antennas is 1.96 dBi. The proposed antenna is efficiently transmitting and receiving signal by generating two opposite beam directions using two RF switches (PIN diode). Also, we investigated how radiation pattern changes according to three angles ($30^{\circ}$, $90^{\circ}$, $150^{\circ}$) of Top Loading. In this paper, we measured and compared the SNR (Signal-to-Noise Ratio) and BER (Bit Error Rate) performances of the proposed antennas in the condition between an ideal environment of anechoic chamber and smart house existing practical electromagnetic interferences (Universal Software Radio Peripheral, USRP). Throughout the comparing the results of the measurement of two cases, we found that the SNR is degraded over 5dB in average and BER is increased over ten times in maximum, therefore, it is confirmed that the error rate of receiving signal is increased. The measured results of SNR and BER value in this paper able to expect the performance degrading by the interference from the electromagnetic devices.

A burst-error-correcting decoding scheme of multiple trellis-coded $\pi$/4 shift QPSK for mobile communication channels (이동 통신 채널에서 다중 트렐리스 부호화된 $\pi$/4 shift QPSK의 연집 에러 정정 복호 방식)

  • 이정규;송왕철;홍대식;강창언
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.4
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    • pp.24-31
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    • 1995
  • In this paper, the dual-mode burst-error-correcting decoding algorithm is adapted to the multiple trellis-coded .pi./4 shift QPSK in order to achieve the improvement of bit error rate (BER) performance over fading channels. The dual-mode adaptive decoder which combines maximum likelihood decoding with a burst detection scheme usually operates as a Viterbi decoder and switches to time diversity error recovery whenever an uncorrectable error pattern is identified. Rayleigh fading channels and Rician fading channels having the Rician parameter K=5dB are used in computer simulation, and the simulation results are compared with those of interleaving techniques. It is shown that under the constraint of the fixed overall memory quantity, the dual-mode adaptive decoding scheme gains an advantage in the BER performance with respect to interleaving strategies.

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