• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.3
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• pp.9-17
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• 2000

In this paper we implement computer simulation system of 4FSK signal MODEM using Quadrature detector and analyze overall tranceiver system. We follow the FLEX wireless paging system standards and construct premodulation filter and data frame. We propose an efficient open loop symbol timing recovery algorithm which takes advantage of 128 bit length preamble pattern and also propose a 32 bit UW pattern which Is based on the optimal UW detection method, and excellent aperiodic autocorrelation characteristic. The BER simulation in the fading channel as well as AWGN is performed with BCH coding and Interleaving to the Quadrature detector system and it is shown that a high coding fain occurs in the fading channel rather than AWGN channel.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.11C
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• pp.1030-1036
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• 2006

In this paper, we present two methods of correcting bit errors in constant amplitude multi-code (CAMC) CDMA, which uses the redundant bits only. The first method is a parity-based bit correction with hard-decision, where the received signals despread into n two-dimensional structure with both horizontal parity and vertical parity. Then, an erroneous bit is corrected for each $4{\times}4$ pattern. The second method is a turbo decoding, which is modified from the decoding of a single parity check product code (SPCPC). Experimental results show that, in the second method, the redundant bits in CAMC can be fully used for the error correction and so they are not really a loss of channel bandwidth. Hence, CAMC provides both a low peak-to-average power ratio and robustness to bit errors.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.1B
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• pp.47-55
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• 2009

In recent network intrusion detection systems, regular expressions are used to represent malicious packets. In order to process incoming packets through high speed networks in real time, we should perform hardware-based pattern matching using the configurable device such as FPGAs. However, operating speed of FPGAs is slower than giga-bit speed network and so, multi-byte processing per clock cycle may be needed. In this paper, we propose a hardware architecture of multi-byte based regular expression pattern matching and implement the pattern matching circuit generator. The throughput improvements in four-byte based pattern matching circuit synthesized in FPGA for several Snort rules are $2.62{\sim}3.4$ times.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.388-396
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• 2012

In this paper, a $320{\times}240$ pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column-counters type, and the frame rate is approximately 40% faster than the double memory type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung $0.13{\mu}m$ 1P4M CMOS process and used a 4T APS with a pixel pitch of $2.25{\mu}m$. The measured column fixed pattern noise (FPN) is 0.10 LSB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.4
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• pp.499-504
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• 2002

In this paper, we analyzed the performance of FH/CPFSK system with differential detection in thermal noise, partial-band jamming noise and adjacent interference of all eight bit pattern. The parameters to analize performances of FH/CPFSK system have been used the bit rate, modulation index and performances of FH/CPFSK system with the differential detector have been presented with the optimum correlation function. And, we were compared with performance of FH/CPFSK and FH/BFSK system. In result, we could know that bit error probability of the approximation equation and exact equation nearly accorded in the high signal-to-noise ratio. And, we have been proved that FH/CPFSK system with differential detection according to jamming fraction ${\gamma}$ was worst to 3dB than FH/CPFSK system with limiter-discriminator. but was superior to 2dB than FH/BFSK.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.2
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• pp.1-9
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• 2012

This study proposed a method to determine the number and location of bus information terminals (BIT), which is a device to provide passengers with bus arrival time at bus stops in a Bus Information System (BIS). In low-density area, it is not efficient to survey bus demands such as the number of passengers at all bus stops due to time and cost. This kind of a survey would, however, competently cover all bus stops if performed inside the bus. The number of riding-on and -off passengers is observed for every bus stop, and this data collection is repeated over all day. Data obtained from the survey are aggregated each bus stop. This study defines Utility Index (UI), an aggregate each bus stop. Bus stops are ranked according to UI and determined for a BIT within budget limitation. As a case study, a bus line in Jeju island, Korea, was dealt with. This case showed that the more aggregate the better data quality. This study is expected to contribute to solving a location problem of BITs in a BIS.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.15 no.4
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• pp.300-304
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• 2015

A low bit rate speech coder based on the non-uniform sampling technique is proposed. The non-uniform sampling technique is based on the detection of inflection points (IP). A speech block is processed by the IP detector, and the detected IP pattern is compared with entries of the IP database. The address of the closest member of the database is transmitted with the energy of the speech block. In the receiver, the decoder reconstructs the speech block using the received address and the energy information of the block. As results, the coder shows fixed data rate contrary to the existing speech coders based on the non-uniform sampling. Through computer simulation, the usefulness of the proposed technique is shown. The SNR performance of the proposed method is approximately 5.27 dB with the data rate of 1.5 kbps.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.10
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• pp.1061-1070
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• 2009

In this paper, we have designed TDL(True-time Delay Line) for eliminating beam-squint occurring in active phased array antenna with large electrical size operated in wide bandwidth, and have tested its electrical performance. The proposed TDL device is composed of 4-bit microstrip delay line structure and MMIC amplifier for compensation of the delay-line loss. The measured results of gain and phase versus delay state satisfy the electrical requirements, also P1dB output power and noise figure meet the requirement. To verify the performance of fabricated TDL, we have simulated the beam patterns of wide-band active phased array antenna using the measured results and have certified the beam pattern compensation performance. As a result of simulated beam pattern compensation with respect to the 675.8 mm size antenna which is operated in X-band, 800 MHz bandwidth, we have reduced the beam squint error of ${\pm}1^{\circ}$ with ${\pm}0.1^{\circ}$. So this TDL module is able to be applied to active phase array antenna system.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.4
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• pp.127-135
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• 1994

In this paper we propose an EWLD(Enhanced Weighted Levenshtein Distance) algorithm to organize code-string pattern matching linear array processor based on the mappting to an one-dimensional array from a two-dimensional matching matrix, and design a processing element(PE) of the processor, N PEs are required instead of NS02T in the processor because of the mapping. Data input and output between PEs and all internal operations of each PE are performed in bit-serial fashion. The bit-serial operation consists of the computing of word distance (WD) by comparison and the selection of optimal code transformation path, and takes 22 clocks as a cycle. The layout of a PE is designed based on the double metal $1.5\mu$m CMOS rule. About 1,800 transistors consistute a processing element and 2 PEs are integrated on a 3mm$\times$3mm sized chip.

• Journal of the Korean Institute of Intelligent Systems
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• v.10 no.4
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• pp.379-389
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• 2000

A cellular automaton is well-known for self-organizing and dynamic behavions in the filed of artifial life. This paper addresses a new neuronic architecture called an evolvable celluar classifier which evolves with the genetic rules (chromosomes) in the non-uniform cellular automata. An evolvable cellular classifier is primarily based on cellular programming, but its mechanism is simpler becaise it utilizes only mutations for the main genetic operators and resmbles the Hopfield network. Therefore, the desirable bit-patterns could be obtained through evolutionary processes for just one individual agent, As a rusult, an evolvable hardware is derived which is applicable to clessification of bit-string information.