• 제목/요약/키워드: 4 wire circuit

검색결과 84건 처리시간 0.024초

S-parameter의 변화를 유도하는 임피던스 변화 감지를 통한 전자회로의 결함검출회로 (The defect detection circuit of an electronic circuit through impedance change detection that induces a change in S-parameter)

  • 서동환;강태엽;유진호;민준기;박창근
    • 전기전자학회논문지
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    • 제25권4호
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    • pp.689-696
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    • 2021
  • 본 논문에서는 고장예측진단 및 건전성 관리 기법(Prognostics and Health Management, PHM)을 적용하기 위해 해당 시스템 혹은 회로 내부에서 결함특성을 감지하고 예측할 수 있는 회로 구조를 제안하였다. 기존 연구에서 회로 결함의 진행에 따라, S-parameter 크기 최소값의 주파수가 변화하는 것을 확인하였다. 이러한 특성을 기존에는 네트워크 분석기(Network Analyzer)를 활용하여 측정하였으나, 본 연구에서는 같은 결함검출기법을 활용하더라도 큰 계측장비 없이 결함의 진행상황 및 잔여 수명, 결함발생 여부를 확인할 수 있는 소형화된 회로를 설계하였다. 본 연구에서는 S-parameter의 변화를 야기하는 임피던스의 변화를 감지할 수 있도록 회로를 설계하였으며, Bond-wire의 온도반복에 따른 S-parameter 변화 측정결과를 제안하는 회로에 적용하였다. 이를 통해 해당 회로가 Bond-wire의 결함을 감지할 수 있다는 것을 성공적으로 검증하였다.

전류방식 CMOS에 의한 ROM 형의 다치 논리 회로 설계 (Design of Multiple Valued Logic Circuits with ROM Type using Current Mode CMOS)

  • 최재석;성현경
    • 전자공학회논문지B
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    • 제31B권4호
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    • pp.55-61
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    • 1994
  • The multiple valued logic(MVL) circuit with ROM type using current mode CMOS is presented in this paper. This circuit is composed of the multiple valued-to-binary(MV/B) decoder and the selection circuit. The MV/B decoder decodes the single input multiple valued signal to N binary signal, and the selection circuits is composed N$\times$N array of the selecion cells with ROM types. The selection cell is realized with the current mirror circuits and the inhibit circuits. The presented circuit is suitable for designing the circuit of MVL functions with independent variables, and reduces the number of selection cells for designing the circuit of symmetric MVL functions as many as {($N^2$-N)/2}+N. This circuit possess features of simplicity. expansibility for array and regularity, modularity for the wire routing. Also, it is suitable for VLSI implementation.

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전용제어회로를 적용한 딥스틱게이지형 소형 엔진열화감지센서 개발 (Development of Dipstick-Gage-Type Small Sensor Equipped with Individual Control Circuit for Detecting Engine Oil Deterioration)

  • 전상명
    • Tribology and Lubricants
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    • 제29권3호
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    • pp.143-148
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    • 2013
  • In this study, several sensor parts used to obtain better signal stability are designed, a separate control circuit for the sensor is developed, and the results obtained using this control circuit are analyzed. The capacitances of the whole sensor system are measured using the control circuit connected to an improved flexible printed circuit board and an asymmetric dual sensor coated with a ceramic material. To realize good discrimination for a small change in the measured capacitance as the engine oil deteriorates, a commercial application-specific integrated circuit is installed on the control circuit as a capacitance-to-digital converter. The absolute error of a measured signal is found to be approximately ${\pm}4fF$.

GMAW에서 와이어 송급속도의 변동이 아크안정성에 미치는 영향에 관한 연구 (Effects of Wire speed Fluctuation on Arc Stability in GMA Welding)

  • 신현욱;최용범;성원호;장희석
    • Journal of Welding and Joining
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    • 제13권4호
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    • pp.85-102
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    • 1995
  • Weld quality of GMA welding processes is closely related to arc stability. Although many researches on arc stability have been performed, real-time estimation of arc stability has not been attempted. For instance, Mita proposed a off-line statistical method in which short circuiting and arcing time, and voltage and current wave forms were sampled to assess arc stability. But this method is not suitable to assess arc stability for GMA welder which employ inverter power source due to its controlled current and voltage wave forms. In this paper, the relationship between are stability and wire feed rate fluctuation is analyzed to propose new criterion for inverter power source. When arc voltage and arc current and arcing time are analyzed, we can assess arc stability only for short circuit transfer mode. When wire feed rate is analyzed, we can estimate arc stability udner the condition of spray transfer mode as well. Hence, the wire feed rate is chosen for monitoring process variable to cover possible metal transfer modes in GMAW. Through this research, it has been identified that arc stability in GMA welding processes is closely related to wire fed rate. When inverter power source is used, conventional statistical method of estimating arc stability, such as Mita index, is no longer valid due to its controlled voltage and current wave forms. Arc stability has been also examined in phase plane diagram.

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과부하 및 물리적 손상(반단선)에 의한 전선의 열적특성 해석 (Analysis for the Thermal Properties of the Electrical Wire according to Overload and Disconnection)

  • 김성철;김두현
    • 한국안전학회지
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    • 제22권4호
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    • pp.26-31
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    • 2007
  • According to the statistical analysis on the electrical fire of 2005 years, most of electrical fire is generated from short circuit(4,985 cases), overcurrent(755 cases) leakage current(391 cases), poor contact(378 cases), disconnection(36 cases) on the electrical wiring device. The researches for the fire hazard about normal electric wiring have already been progressing in the advanced country such as USA and Japan, but Comparative study of the disconnection has not been conducted. Therefore, in this paper, we have simulated the thermal analysis for electrical wire according to deteriorating time in a normal state and disconnection with electrical wire using the electrical-thermal finite element method(Flux 3D). This paper acquire basis data of electricity fire signal by disconnection and wish to help for electrical fire cause diagnosis business.

PR 제어기를 이용한 3상 4선식 인버터 Neutral Leg 제어 방법 (Control of the Neutral Leg in Three-Phase Four-Wire Inverter Using Proportional-Resonant Controller)

  • 한정호;송중호
    • 조명전기설비학회논문지
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    • 제29권2호
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    • pp.54-61
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    • 2015
  • In 3-phase 4-wire inverter, the unbalanced loads cause to increase the neutral current which brings the voltage deviation between the split dc-link capacitors to be larger. In order to solve this problem, a neutral leg is provided additively to the ordinary inverter circuit and the associated control methods are devised. This paper proposes a new neutral-leg controller based on a PR controller and shows relatively good performance even under unbalanced linear loads and nonlinear loads. The proposed control strategy illustrates its effectiveness under the various operating conditions through simulation works.

2중주파 합성시험회로의 TRV 패턴 분류 및 파라미터 계산 방법 (TRV Pattern Classification and Parameter Calculation Method for Double-Frequency Synthetic Test Circuit)

  • 이용한
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2004년도 하계학술대회 논문집 A
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    • pp.587-589
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    • 2004
  • In this paper analytical pattern classification of TRV waves created by double-frequency synthetic test circuit was proposed. According to the classified patterns of the TRV wave, calculation methods of 3 reference lines and 4 parameters characterizing the TRV wave wire proposed. These methods can be utilized to optimize test facility and to standardize test quality.

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와이어 소잉 데미지 층이 단결정 실리콘 태양전지 셀 특성에 미치는 영향 (Relation Between Wire Sawing-damage and Characteristics of Single Crystalline Silicon Solar-cells)

  • 김일환;박준성;박재근
    • Current Photovoltaic Research
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    • 제6권1호
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    • pp.27-30
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    • 2018
  • The dependency of the electrical characteristics of silicon solar-cells on the depth of damaged layer induced by wire-sawing process was investigated. To compare cell efficiency with residual sawing damage, silicon solar-cells were fabricated by using as-sawn wafers having different depth of saw damage without any damaged etching process. The damaged layer induced by wire-sawing process in silicon bulk intensely influenced the value of fill factor on solar cells, degrading fill factor to 57.20%. In addition, the photovoltaic characteristics of solar cells applying texturing process shows that although the initial depth of saw-damage induced by wire-sawing process was different, the value of short-circuit current, fill-factor, and power-conversion-efficiency have an almost same, showing ~17.4% of cell efficiency. It indicated that the degradation of solar-cell efficiency induced by wire-sawing process could be prevented by eliminating all damaged layer through sufficient pyramid-surface texturing process.

간이 승강기 수·자동 배선제어방식에 관한 연구 (A Study on the Wiring Control Method of Hand & Auto Operation of an Easy Elevator)

  • 위성동;구할본
    • 한국전기전자재료학회논문지
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    • 제16권4호
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    • pp.351-357
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    • 2003
  • An easy learning elevator originated is opened to compare the existed teaming equipment, and it had a high studied efficiency that the sequence control circuit can open and close with the wire. The structure of equipment to be controlled from the first floor to the fifth floors is demostrated by the constructive apparatus with the lamps to express the function of the open-close of the door according to the cage moving with a mechanical actuation of the forward reverse breaker and the motor of load, and the mechanical actuation of hand-operation control components of push-button S/W and L/S and relay etc. These components let connect each other in order to control of the elevator function with the auto program and the designed sequence control circuit. Consequently the cage could go and come till 1∼5 steps with an auto program of the elevator and the sequence control circuit. The sequence control circuit is controlled by the step of forward and reverse to follow as that the sensor function of L/S1 ∼ L/S5 let posit with the control switchs of S/W1 ∼ S/W5 of PLC testing panel and switchs of S/W1 ∼ S/W5 installed on the transparent acryl plate of the frame. In here, improved apparatus is the hand-auto operation combined learning equipment to study the principle and technique of the originate sequence control circuit and the auto program of PLC.

IGBT Open-Circuit Fault Diagnosis for 3-Phase 4-Wire 3-Level Active Power Filters based on Voltage Error Correlation

  • Wang, Ke;Tang, Yi;Zhang, Xiao;Wang, Yang;Zhang, Chuan-Jin;Zhang, Hui
    • Journal of Power Electronics
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    • 제16권5호
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    • pp.1950-1963
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    • 2016
  • A novel open-circuit fault diagnosis method for 3-phase 4-wire 3-level active power filters based on voltage error correlation is proposed in this paper. This method is based on observing the output pole voltage error of the active power filter through two kinds of algorithms. One algorithm is a voltage error analytical algorithm, which derives four output voltage error analytic expressions through the pulse state, current value and dc bus voltage, respectively, assuming that all of the IGBTs of a certain phase come to an OC fault. The other algorithm is a current circuit equation algorithm, which calculates the real-time output voltage error through basic circuit theory. A correlation is introduced to measure the similarity of the output voltage errors between the two algorithms, and OC faults are located by the maximum of the correlations. A FPGA has been chosen to implement the proposed method due to its fast prototyping. Simulation and experimental results are presented to show the performance of the proposed OC fault diagnosis method.