• 한국전자통신학회논문지
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• 제14권3호
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• pp.467-474
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• 2019

본 논문에서는 마이크로스트립 안테나의 대역폭을 넓히기 위해 많이 사용되는 적층형 구조를 연구하였다. 두 패치간 거리에 따른 특성을 분석하고 주 패치 급전 선로에 병렬 개방 스터브를 연결하여 임피던스 정합을 최적화하였다. 병렬 스터브는 기생 패치와 접지면 사이로 이루어지는 영역 내부에 삽입되므로 정합회로를 위한 별도의 공간이 필요하지 않아서 소형화에 유리한 구조이다. 여러 가지 파라미터들이 안테나 특성에 미치는 영향을 분석하고, 제안된 구조의 안테나를 2.3~2.7GHz 대역에 적합하도록 최적화하였다. 실험 결과, 제안한 안테나의 주파수대역은 2.27~2.75GHz로써 대역폭은 약 480MHz이며, 스터브가 없는 스택 구조 안테나에 비해 약 160MHz의 광대역 특성을 얻었다. 안테나 이득은 대역폭 내에서 2.3GHz에서 최소 5.8dBi, 최대 2.6GHz에서 7.8dBi를 얻었다.

• 마이크로전자및패키징학회지
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• 제27권1호
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• pp.17-24
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• 2020

As an interconnect scaling faces a technical bottleneck, the device stacking technologies have been developed for miniaturization, low cost and high performance. To manufacture a stacked device structure, a vertical interconnect becomes a key process to enable signal and power integrities. Most bonding materials used in stacked structures are currently solder or Cu pillar with Sn cap, but copper is emerging as the most important bonding material due to fine-pitch patternability and high electrical performance. Copper bonding has advantages such as CMOS compatible process, high electrical and thermal conductivities, and excellent mechanical integrity, but it has major disadvantages of high bonding temperature, quick oxidation, and planarization requirement. There are many copper bonding processes such as dielectric bonding, copper direct bonding, copper-oxide hybrid bonding, copper-polymer hybrid bonding, etc.. As copper bonding evolves, copper-oxide hybrid bonding is considered as the most promising bonding process for vertically stacked device structure. This paper reviews current research trends of copper bonding focusing on the key process of Cu-SiO₂ hybrid bonding.

• 마이크로전자및패키징학회지
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• 제21권2호
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• pp.43-51
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• 2014

3차원 적층 패키지(3D integrated package) 에서 초소형 패키지 내에 적층되어 있는 칩들의 발열로 인한 열 신뢰성 문제는 3차원 적층 패키지의 핵심 이슈가 되고 있다. 본 연구에서는 TSV(through-silicon-via) 기술을 이용한 3차원 적층 패키지의 열 특성을 분석하기 위하여 수치해석을 이용한 방열 해석을 수행하였다. 특히 모바일 기기에 적용하기 위한 3D TSV 패키지의 열 특성에 대해서 연구하였다. 본 연구에서 사용된 3차원 패키지는 최대 8 개의 메모리 칩과 한 개의 로직 칩으로 적층되어 있으며, 구리 TSV 비아가 내장된 인터포저(interposer)를 사용하여 기판과 연결되어 있다. 실리콘 및 유리 소재의 인터포저의 열 특성을 각각 비교 분석하였다. 또한 본 연구에서는 TSV 인터포저를 사용한 3D 패키지에 대해서 메모리 칩과 로직 칩을 사용하여 적층한 경우에 대해서 방열 특성을 수치 해석적으로 연구하였다. 적층된 칩의 개수, 인터포저의 크기 및 TSV의 크기가 방열에 미치는 영향에 대해서도 분석하였다. 이러한 결과를 바탕으로 메모리 칩과 로직 칩의 위치 및 배열 형태에 따른 방열의 효과를 분석하였으며, 열을 최소화하기 위한 메모리 칩과 로직 칩의 최적의 적층 방법을 제시하였다. 궁극적으로 3D TSV 패키지 기술을 모바일 기기에 적용하였을 때의 열 특성 및 이슈를 분석하였다. 본 연구 결과는 방열을 고려한 3D TSV 패키지의 최적 설계에 활용될 것으로 판단되며, 이를 통하여 패키지의 방열 설계 가이드라인을 제시하고자 하였다.

• Current Optics and Photonics
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• 제5권1호
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• pp.23-31
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• 2021

We propose a wheel screen type Lamina 3D display, which realizes a 3D image that can satisfy the accommodation cue by projecting volumetric images encoded by varying polarization states to a multilayered screen. The proposed system is composed of two parts: an encoding part that converts depth information to states of polarization and a decoding part that projects depth images to the corresponded diffusing layer. Though the basic principle of Lamina displays has already been verified by previous studies, those schemes suffered from a bottleneck of inferior resolution of the 3D image due to the blurring on the surfaces of diffusing layers in the stacked volume. In this paper, we propose a new structure to implement the decoding part by adopting a form of the wheel screen. Experimental verification is also provided to support the proposed principle.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.545-546
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• 2008

This paper presents a low power CMOS low noise amplifier for UWB applications. To reduce the power consumption, two cascode amplifiers was stacked in DC. Designed with $0.18-{\mu}m$ CMOS technology, the proposed LNA achieves 20dB flat gain, below 3dB noise figure, and the power consumption of 5.2mW from a 1.8 V supply voltage.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.595-596
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• 2006

A novel Si via structure is suggested and fabricated for 3D MEMS package using the doped silicon as an interconnection material. Oxide isolations which define Si via are formed simultaneously when fabricating the MEMS structure by using DRIE and oxidation. Silicon Direct Bonding Multi-stacking process is used for stacked package, which consists of a substrate, MEMS structure layer and a cover layer. The bonded wafers are thinned by lapping and polishing. A via with the size of $20{\mu}m$ is fabricated and the electrical and mechanical characteristics of via are under testing.

• 한국복합재료학회:학술대회논문집
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• 한국복합재료학회 2005년도 춘계학술발표대회 논문집
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• pp.71-75
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• 2005

For the damage tolerance improvement of conventional laminated composites, stitching process have been utilized for providing through-thickness reinforcements. 2D preforms were stacked with S-2 glass plain weave and S-2 glass MWK (Multi-axial Warp Knit) L type. 3D preforms were fabricated using the stitching process. All composite samples were fabricated by RTM (Resin Transfer Molding) process. To examine the damage resistance performance the low speed drop weight impact test has been carried out. For the assessment of damage after the impact loading, specimens were examined by scanning image. CAI (Compressive After Impact) tests were also conducted to evaluate residual compressive strength. Compared with 2D composites, the damage area of 3D composites was reduced by 20-30% and the CAI strength showed 5-10% improvement.

• Journal of Information Processing Systems
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• 제16권2호
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• pp.343-359
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• 2020

In this paper, a new algorithm is proposed for three-dimensional (3D) shape recognition using local features of model views and its sparse representation. The algorithm starts with the normalization of 3D models and the extraction of 2D views from uniformly distributed viewpoints. Consequently, the 2D views are stacked over each other to from view cubes. The algorithm employs the descriptors of 3D local features in the view cubes after applying Gabor filters in various directions as the initial features for 3D shape recognition. In the training stage, we store some 3D local features to build the prototype dictionary of local features. To extract an intermediate feature vector, we measure the similarity between the local descriptors of a shape model and the local features of the prototype dictionary. We represent the intermediate feature vectors of 3D models in the sparse domain to obtain the final descriptors of the models. Finally, support vector machine classifiers are used to recognize the 3D models. Experimental results using the Princeton Shape Benchmark database showed the average recognition rate of 89.7% using 20 views. We compared the proposed approach with state-of-the-art approaches and the results showed the effectiveness of the proposed algorithm.

• Current Photovoltaic Research
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• 제7권1호
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• pp.1-8
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• 2019

The $Cu(In,Ga)Se_2$ (CIGS) thin film obtained by two-step process (metal deposition and Se annealing) has a rough surface morphology and many voids at the CIGS/Mo interface. To solve the problem a precursor that contains Se was employer by depositing a (In,Se)/(Cu,Ga) stacked layer. We devised a two-step annealing (vacuum pre-annealing and Se annealing) for the precursor because direct annealing of the precursor in Se environment resulted in the small grains with unwanted demarcation between stacked layers. After vacuum pre-annealing up to $500^{\circ}C$ the CIGS film consisted of CIGS phase and secondary phases including $In_4Se_3$, InSe, and $Cu_9(In,Ga)_4$. The secondary phases were completely converted to CIGS phase by a subsequent Se annealing. A void-free CIGS/Mo interface was obtained by the two-step annealing process. Especially, the CIGS film prepared by vacuum annealing $450^{\circ}C$ and subsequent Se annealing $550^{\circ}C$ showed a densely-packed grains with smooth surface, well-aligned bamboo grains on the top of the film, little voids in the film, and also little voids at the CIGS/Mo interface. The smooth surface enhanced the cell performance due to the increase of shunt resistance.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.220-220
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• 2012

The supercapacitors with extraordinarily high capability for energy storage are attracting growing attention for their potential applications in portable electronic equipments, hybrid vehicles, cellular devices, and so on. The nanostructuring of the electrode surface can provide large surface area and consequently easy diffusion of ions in the capacitors. In addition, compared to two-dimensional nanostructures, the three-dimensional (3D) nano-architecture is expected to lead to significant enhancement of mechanical and electrical properties such as capacitance per unit area of the electrode. Polyaniline (PANi) is known as promising electrode material for supercapacitors due to its desirable properties such as high electro activity, high doping level and environmental stability. In this context, we fabricated well-ordered 3D PANi nanostructures on 3D polystyrene (PS) nanospheres which was arrayed by layer-by-layer stacking method. The height of the PANi nanostructures could be controlled by the number of PS layers stacked. 3D PANi hollow nanospheres were also fabricated by dissolving inner PS nanospheres, which resulted in further enhancement of the surface area and capacitance of the electrode.