• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2017년도 춘계학술대회
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• pp.200-201
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• 2017

이 논문은 3D 순차적 CMOS 인버터 회로의 전기적 상호작용을 고려한 시뮬레이션을 제시하고자 한다. 상층 NMOS는 BSIM-IMG, 하층 PMOS에는 LETI-UTSOI 모델을 사용하여 전기적 상호작용이 잘 반영되는지 TCAD 데이터와 SPICE 데이터를 비교하였다. 트랜지스터 간의 높이가 작을 때 하층 게이트의 전압의 변화에 따라 상층 전류-전압 특성에 전기적 상호작용이 잘 반영되는 것을 확인하였다.

• 한국기계가공학회지
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• 제14권3호
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• pp.15-20
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• 2015

After the US government declared 3D printing technology a next-generation manufacturing technology, there have been many practical studies conducted to expand 3D printing technology to manufacturing technologies, called AMERICA MAKES. In particular, the Keck Center, located at the University of Texas at El Paso, has studied techniques for easily combing the 3D stacking process with space mobility and expanded these techniques to simultaneous staking techniques for multiple materials. Additionally, it developed convergence manufacturing techniques, such as direct inking techniques, in order to produce a module structure that combines electronic circuits and components, such as CUBESET. However, in these studies, it is impossible to develop a unified system using traditional independent through simple sequencing connections. This is because there are many problems in the integration between the stacking modeling of 3D printers and post-machining, such as thermal deformations, the precision accuracy of 3D printers, and independently driven coordinate problems among process systems. Therefore, in this paper, the integration method is suggested, which combines these 3D printers and subsequent machining process systems through an Internet-based cloud. Additionally, the sequential integrated system of a 3D printer, an NC milling machine, machine vision, and direct inking are realized.

• 한국정보통신학회논문지
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• 제19권12호
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• pp.2899-2904
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• 2015

3차원 순차적 집적회로에서 열에 의한 손상으로 생성되는 계면 포획 전하가 트랜지스터의 드레인 전류-게이트 전압 특성에 미치는 영향을 소개한다. 2차원 소자 시뮬레이터를 이용해서 산화막 층에 계면 포획 전자 분포를 추출한 결과를 설명한다. 이 계면 포획 전자분포를 고려한 3차원 순차적 집적회로에서 Inter Layer Dielectric (ILD)의 길이에 따른 하층 트랜지스터의 게이트 전압의 변화에 따라서 상층 트랜지스터의 문턱전압 $V_{th}$의 변화량에 대해서 소개한다. 상대적으로 더 늦은 공정인 상층 $HfO_2$층 보다 하층 $HfO_2$층과 양쪽 $SiO_2$층이 열에 의한 영향을 더 많이 받았다. 계면 포획 전하 밀도 분포를 사용하지 않았을 때 보다 사용 했을 때 $V_{th}$ 변화량이 더 적게 변하는 것을 확인 했다. 3차원 순차적 인버터에서 ILD의 길이가 50nm이하로 짧아질수록 점점 더 $V_{th}$ 변화량이 급격히 증가하였다.

• Journal of information and communication convergence engineering
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• 제12권3호
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• pp.186-192
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• 2014

Monolithic three-dimensional integrated chips (3D ICs) are an emerging technology that offers an integration density that is some orders of magnitude higher than the conventional through-silicon-via (TSV)-based 3D ICs. This is due to a sequential integration process that enables extremely small monolithic inter-tier vias (MIVs). For a monolithic 3D memory, we first explore the static random-access memory (SRAM) design. Next, for digital logic, we explore several design styles. The first is transistor-level, which is a design style unique to monolithic 3D ICs that are enabled by the ultra-high-density of MIVs. We also explore gate-level and block-level design styles, which are available for TSV-based 3D ICs. For each of these design styles, we present techniques to obtain the graphic database system (GDS) layouts, and perform a signoff-quality performance and power analysis. We also discuss various challenges facing monolithic 3D ICs, such as achieving 50% footprint reduction over two-dimensional (2D) ICs, routing congestion, power delivery network design, and thermal issues. Finally, we present design techniques to overcome these challenges.

• Geomechanics and Engineering
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• 제34권1호
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• pp.29-41
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• 2023

The 3D geospatial modeling of geotechnical information can aid in understanding the geotechnical characteristic values of the continuous subsurface at construction sites. In this study, a geostatistical optimization model for the three-dimensional (3D) mapping of subsurface stratification and the SPT-N value based on a trial-and-error rule was developed and applied to a dam emergency spillway site in South Korea. Geospatial database development for a geotechnical investigation, reconstitution of the target grid volume, and detection of outliers in the borehole dataset were implemented prior to the 3D modeling. For the site-specific subsurface stratification of the engineering geo-layer, we developed an integration method for the borehole and geophysical survey datasets based on the geostatistical optimization procedure of ordinary kriging and sequential Gaussian simulation (SGS) by comparing their cross-validation-based prediction residuals. We also developed an optimization technique based on SGS for estimating the 3D geometry of the SPT-N value. This method involves quantitatively testing the reliability of SGS and selecting the realizations with a high estimation accuracy. Boring tests were performed for validation, and the proposed method yielded more accurate prediction results and reproduced the spatial distribution of geotechnical information more effectively than the conventional geostatistical approach.

• Journal of Information Display
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• 제4권4호
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• pp.4-7
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• 2003

The world largest 21.3" LTPS LCD has been successfully developed using SLS crystallization technology. Integration of gate circuit, transmission gate and level shifter was successfully performed in a large area display. Uniform and high performance of high quality grains of SLS technology make it possible to realize a uniform large size LTPS TFT-LCD with half the number of data driver IC's that is typically used in a-Si LCD. High aperture ratio of 65 % was achieved using an organic inter insulating method which lead to a high brightness of 500 cd/$cm^2$.

• 한국항행학회논문지
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• 제24권3호
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• pp.184-191
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• 2020

항공용 SIL은 항공전자시스템의 통합 및 검증에 사용되는 통합시험환경이다. 항공용 SIL에는 여러 가지 제약으로 인해 항공기에 탑재되는 장비를 직접 연동할 수 없을 때 장비의 소프트웨어 모델이 필요하다. 지금까지 항공기 개발에 적용한 항공용 SIL의 소프트웨어 모델은 표준화된 방법 없이 일반적인 소프트웨어 개발 방법의 적용으로 재사용이 어려워 소프트웨어 모델 재사용을 위한 프레임워크의 필요성이 제기되었다. 이러한 항공용 SIL 모델의 표준화된 모델링 방법을 위해 DEVS (discrete event system specification) 형식론을 채용하였다. DEVS 형식론은 이벤트 구동(event-driven) 알고리즘이며 이는 기존의 항공용 SIL에 적용되는 절차적이고 반복적인 알고리즘과 어울려 동작하기 힘들다. 이에 본 논문에서는 항공용 SIL 모델의 특징과 기존 방식이 가지는 한계를 보완하고 모델의 재사용성을 극대화할 수 있는 이벤트 기반의 모델링 방법과 실시간 시뮬레이션 방법을 제안한다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.241-244
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• 2003

The world largest 21.3" LTPS LCD has been successfully developed using SLS crystallization technology. Successful integration of gate circuit, transmission gate and level shifter was performed in a large area uniformly. Uniformity and high performance from high quality grains of SLS technology make it possible to come true a uniform large size LTPS TFT-LCD with half number of data driver IC's used in typical a-Si LCD. High aperture ratio of 65% was obtained using an organic inter insulating method, which lead a high brightness of 500cd/cm2.

• 로봇학회논문지
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• 제7권2호
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• pp.92-100
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• 2012

A map of complex environment can be generated using a robot carrying sensors. However, representation of environments directly using the integration of sensor data tells only spatial existence. In order to execute high-level applications, robots need semantic knowledge of the environments. This research investigates the design of a system for recognizing objects in 3D point clouds of urban environments. The proposed system is decomposed into five steps: sequential LIDAR scan, point classification, ground detection and elimination, segmentation, and object classification. This method could classify the various objects in urban environment, such as cars, trees, buildings, posts, etc. The simple methods minimizing time-consuming process are developed to guarantee real-time performance and to perform data classification on-the-fly as data is being acquired. To evaluate performance of the proposed methods, computation time and recognition rate are analyzed. Experimental results demonstrate that the proposed algorithm has efficiency in fast understanding the semantic knowledge of a dynamic urban environment.

• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2002년도 춘계 학술대회논문집
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• pp.47-52
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• 2002

The supersonic flow around multi-stage rocket system is analyzed using 3-D compressible unsteady flow solver. A Chimera overset grid technique is used for the calculation of present configuration and grid around the core rocket is composed of 3 zones to represent fins in the core rocket. Flow solver is parallelized to reduce the computation time, and an efficient parallelization algorithm for Chimera grid technique is proposed. AUSMPW+ scheme is used for the spatial discretization and LU-SGS for the time integration. The flow field around multi-stage rocket was analyzed using this developed solver, and the results were compared with that of a sequential solver The speed-up ratio and the efficiency were measured in several processors. As a result, the computing speed with 12 processors was about 10 times faster than that of a sequential solver. Developed flow solver is used to predict the trajectory of booster in separation stage. From the analyses, booster collides against core rocket in free separation case. So, additional jettisoning forces and moments needed for a safe separation are examined.