• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.200-201
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• 2017

This paper introduces the SPICE simulation results of 3D sequential inverter considering electrical coupling. TCAD data and the SPICE data are compared to verify that the electrical coupling is well considered by using BSIM-IMG for the upper NMOS and LETI-UTSOI model for the lower PMOS. When inter layer dielectric is small, it is confirmed that electrical coupling is well reflected in the top transistor $I_{ds}-V_{gs}$ characteristics according to the change of the bottom transistor gate voltage.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.14 no.3
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• pp.15-20
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• 2015

After the US government declared 3D printing technology a next-generation manufacturing technology, there have been many practical studies conducted to expand 3D printing technology to manufacturing technologies, called AMERICA MAKES. In particular, the Keck Center, located at the University of Texas at El Paso, has studied techniques for easily combing the 3D stacking process with space mobility and expanded these techniques to simultaneous staking techniques for multiple materials. Additionally, it developed convergence manufacturing techniques, such as direct inking techniques, in order to produce a module structure that combines electronic circuits and components, such as CUBESET. However, in these studies, it is impossible to develop a unified system using traditional independent through simple sequencing connections. This is because there are many problems in the integration between the stacking modeling of 3D printers and post-machining, such as thermal deformations, the precision accuracy of 3D printers, and independently driven coordinate problems among process systems. Therefore, in this paper, the integration method is suggested, which combines these 3D printers and subsequent machining process systems through an Internet-based cloud. Additionally, the sequential integrated system of a 3D printer, an NC milling machine, machine vision, and direct inking are realized.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.12
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• pp.2899-2904
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• 2015

This paper introduces about the effect on $I_{DS}-V_{GS}$ characteristic of transistor that interface trap charge is created by damage due to heat in a 3D sequential inverter. A interface trap charge distribution in oxide layer in a 3D sequential inverter is extracted using two-dimensional device simulator. The variation of threshold voltage of top transistor according to the gate voltage variation of bottom transistor is also described in terms of Inter Layer Dielectric (ILD) length of 3D sequential inverter, considering the extracted interface trap charge distribution. The extracted interface trap density distribution shows that the bottom $HfO_2$ layer and both the bottom and top $SiO_2$ layer were relatively more affected by heat than the top $HfO_2$ layer with latest process. The threshold voltage variations of the shorter length of ILD in 3D sequential inverter under 50nm is higher than those over 50nm. The $V_{th}$ variation considering the interface trap charge distribution changes less than that excluding it.

• Journal of information and communication convergence engineering
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• v.12 no.3
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• pp.186-192
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• 2014

Monolithic three-dimensional integrated chips (3D ICs) are an emerging technology that offers an integration density that is some orders of magnitude higher than the conventional through-silicon-via (TSV)-based 3D ICs. This is due to a sequential integration process that enables extremely small monolithic inter-tier vias (MIVs). For a monolithic 3D memory, we first explore the static random-access memory (SRAM) design. Next, for digital logic, we explore several design styles. The first is transistor-level, which is a design style unique to monolithic 3D ICs that are enabled by the ultra-high-density of MIVs. We also explore gate-level and block-level design styles, which are available for TSV-based 3D ICs. For each of these design styles, we present techniques to obtain the graphic database system (GDS) layouts, and perform a signoff-quality performance and power analysis. We also discuss various challenges facing monolithic 3D ICs, such as achieving 50% footprint reduction over two-dimensional (2D) ICs, routing congestion, power delivery network design, and thermal issues. Finally, we present design techniques to overcome these challenges.

• Geomechanics and Engineering
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• v.34 no.1
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• pp.29-41
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• 2023

The 3D geospatial modeling of geotechnical information can aid in understanding the geotechnical characteristic values of the continuous subsurface at construction sites. In this study, a geostatistical optimization model for the three-dimensional (3D) mapping of subsurface stratification and the SPT-N value based on a trial-and-error rule was developed and applied to a dam emergency spillway site in South Korea. Geospatial database development for a geotechnical investigation, reconstitution of the target grid volume, and detection of outliers in the borehole dataset were implemented prior to the 3D modeling. For the site-specific subsurface stratification of the engineering geo-layer, we developed an integration method for the borehole and geophysical survey datasets based on the geostatistical optimization procedure of ordinary kriging and sequential Gaussian simulation (SGS) by comparing their cross-validation-based prediction residuals. We also developed an optimization technique based on SGS for estimating the 3D geometry of the SPT-N value. This method involves quantitatively testing the reliability of SGS and selecting the realizations with a high estimation accuracy. Boring tests were performed for validation, and the proposed method yielded more accurate prediction results and reproduced the spatial distribution of geotechnical information more effectively than the conventional geostatistical approach.

• Journal of Information Display
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• v.4 no.4
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• pp.4-7
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• 2003

The world largest 21.3" LTPS LCD has been successfully developed using SLS crystallization technology. Integration of gate circuit, transmission gate and level shifter was successfully performed in a large area display. Uniform and high performance of high quality grains of SLS technology make it possible to realize a uniform large size LTPS TFT-LCD with half the number of data driver IC's that is typically used in a-Si LCD. High aperture ratio of 65 % was achieved using an organic inter insulating method which lead to a high brightness of 500 cd/$cm^2$.

• Journal of Advanced Navigation Technology
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• v.24 no.3
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• pp.184-191
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• 2020

Avionics System Integration Laboratory is the integrated test environment for integration and verification of avionics systems. When real equipment can not be used in the laboratory for various reasons, software models should be needed. Because there hasn't been any standardized method for the models so that it is difficult to reuse the developed models, the need for a framework to develop the avionics software models was emerged. We adopted DEVS(discrete event system specification) formalism as the standardized modeling method for the avionics software models. Due to DEVS formalism is based on event-driven algorithm, it doesn't accord a legacy system which has sequential and periodic algorithms. In this paper, we propose real-time event-driven modeling and simulation method for SIL to overcome these restrictions and to maximize reusability of avionics models through the analysis of the characteristics and the limitations of avionics models.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.241-244
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• 2003

The world largest 21.3" LTPS LCD has been successfully developed using SLS crystallization technology. Successful integration of gate circuit, transmission gate and level shifter was performed in a large area uniformly. Uniformity and high performance from high quality grains of SLS technology make it possible to come true a uniform large size LTPS TFT-LCD with half number of data driver IC's used in typical a-Si LCD. High aperture ratio of 65% was obtained using an organic inter insulating method, which lead a high brightness of 500cd/cm2.

• The Journal of Korea Robotics Society
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• v.7 no.2
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• pp.92-100
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• 2012

A map of complex environment can be generated using a robot carrying sensors. However, representation of environments directly using the integration of sensor data tells only spatial existence. In order to execute high-level applications, robots need semantic knowledge of the environments. This research investigates the design of a system for recognizing objects in 3D point clouds of urban environments. The proposed system is decomposed into five steps: sequential LIDAR scan, point classification, ground detection and elimination, segmentation, and object classification. This method could classify the various objects in urban environment, such as cars, trees, buildings, posts, etc. The simple methods minimizing time-consuming process are developed to guarantee real-time performance and to perform data classification on-the-fly as data is being acquired. To evaluate performance of the proposed methods, computation time and recognition rate are analyzed. Experimental results demonstrate that the proposed algorithm has efficiency in fast understanding the semantic knowledge of a dynamic urban environment.

• 한국전산유체공학회:학술대회논문집
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• 2002.05a
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• pp.47-52
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• 2002

The supersonic flow around multi-stage rocket system is analyzed using 3-D compressible unsteady flow solver. A Chimera overset grid technique is used for the calculation of present configuration and grid around the core rocket is composed of 3 zones to represent fins in the core rocket. Flow solver is parallelized to reduce the computation time, and an efficient parallelization algorithm for Chimera grid technique is proposed. AUSMPW+ scheme is used for the spatial discretization and LU-SGS for the time integration. The flow field around multi-stage rocket was analyzed using this developed solver, and the results were compared with that of a sequential solver The speed-up ratio and the efficiency were measured in several processors. As a result, the computing speed with 12 processors was about 10 times faster than that of a sequential solver. Developed flow solver is used to predict the trajectory of booster in separation stage. From the analyses, booster collides against core rocket in free separation case. So, additional jettisoning forces and moments needed for a safe separation are examined.