• 한국CDE학회논문집
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• 제11권6호
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• pp.429-439
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• 2006

The purpose of this study is to support the integration from current 2D drawing-based design to future 3D model-based design. In this paper, an important theme is the combination between the STEP-based 2D drawing standards (i.e., AP202) and the IFC-based 3D building model standards. To achieve the purpose, two methodologies are proposed as follows: the development of IFC extension model for the 2D shape data representation by harmonizing ISO/STEP AP202; and the development of mapping solution between IFC 2D extension model and KOSDIC by constructing the exchange scenario for 2D shape data representation. It is expected that the proposed IFC2X2 2D extension model and mapping solution will offer the basis of development of the integrated standards model in AEC industry.

• ETRI Journal
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• 제34권5호
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• pp.706-712
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• 2012

In previous work, novel maskless bumping and no-flow underfill technologies for three-dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low-volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no-flow underfill material named "fluxing underfill" is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two-tier stacked TSV chips are sucessfully stacked.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.203-207
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• 1999

In this paper we report new integration technology developed for three-dimensional metallic microstructures in an arbitrary shape. We have developed the two fabrication methods: Multi-Exposure and Single-Development (MESD) and Sacrificial Metallic Mold(SMM) techniques. Three-dimensional photoresist mold can be formed by the MESD method while unlimited number of structural levels can be realized by the SMM technique. Using these two techniques we have fabricated solenoid inductors and levitated spiral inductors for RF applications. We have achieved peak Q- factors over 40 in the 2-10㎓ range, the highest number among the inductors reported to date. Finally, we propose "On-Chip Passives" as a post IC process for monolithic integration of inductors, tunable capacitors, microwave switches, transmission lines, and mixers and filters toward future single-chip transceiver integration.

• 한국멀티미디어학회논문지
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• 제21권8호
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• pp.1021-1026
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• 2018

3D SCAN enables easy human body measurement via a digital method in the process of film costume production which used to be done manually. Software-oriented computer graphic, which integrates 3D SCAN data in the process of manual film costume production, can induce quick and diverse design outcomes. While, 3D PRINT, which integrates computer graphic data in the process of manual film costume production, can automate the process of special costume production using a digital method. Integration of 3D Scan + Computer Graphic + 3D Print using integrated platforms for tailored costume production as developed in this study allows significant reduction of costume production period and costs. It also allows efficient integration of costume production outcomes in various industries related with OSMU contents in particular. In other words, using it, we can create a new business market that integrates multiple areas of film content, drama content and game content.

• 한국CDE학회논문집
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• 제20권2호
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• pp.145-158
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• 2015

ISO 15926 is an international standard for the sharing and integration of plant lifecycle information. Plant design data consist of logical configuration, equipment specifications, 2D piping and instrument diagrams (P&IDs), and 3D plant models (shape data). Although 3D computer-aided design (CAD) data is very important data across the plant lifecycle, few studies on the exchange of 3D CAD data using ISO 15926 have been conducted so far. For this, we analyze information requirements regarding plant 3D design in the process industry. Based on the analysis, ISO 15926 templates are defined for the representation of constructive solid geometry (CSG) - based 3D design data. Since system environments for 3D CAD modeling and Semantic Web technologies are different from each other, we present system architecture for processing and visualizing plant 3D design data in the Web Ontology Language (OWL) format. Through the visualization test of ISO 15926-based 3D design data for equipment with a prototype system, feasibility of the proposed method is verified.

• 한국콘텐츠학회:학술대회논문집
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• 한국콘텐츠학회 2007년도 추계 종합학술대회 논문집
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• pp.530-534
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• 2007

유동 가시화란 가시화 기술의 한 영역으로, 벡터 데이터를 2차원 또는 3차원의 형태로 시각적으로 표출하는 것을 말한다. 즉, 일반적으로 벡터 데이터는 (x, y, z)의 형식으로 이루어져 있는 수열의 집합인데, 이를 사람이 그 특징을 쉽게 인지할 수 있도록 그림 또는 애니메이션으로 표시하는 것을 말한다. 유동 가시화는 가시화 기법, 대상 데이터의 차원, 대상 유동의 종류 등 여러 가지 기준으로 분류가 가능하다. 가시화 기법은 크게 직접 기법, 인티그레이션(integration) 기법, 파생 데이터 기반 기법 등으로 나눌 수 있고, 데이터의 차원은 2차원, 2.5차원, 3차원 등으로 구분할 수 있으며, 유동의 종류는 일정한(steady) 유동과 불규칙한(unsteady) 유동으로 나눌 수 있다. 이러한 유동 가시화는 그 종류가 매우 많고 다양한데, 본 논문에서는 대표적인 인티그레이션 기법인 LIC 기법에 초점을 맞추고 각 기법들을 데이터의 차원으로 분류하고 각 기법의 장단점을 논하고자 한다.

• 한국추진공학회지
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• 제25권3호
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• pp.81-88
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• 2021

아음속 순항 유도탄의 추진시스템은 소형 가스터빈 엔진을 중심으로 공기흡입관, 탄내 연료이송계통 등으로 구성된다. 이는 엔진의 수락시험으로부터 시작하여, 엔진의 여러 기능 및 보기류의 설계수정, 엔진과 연동되는 각종 탄내 장비들의 설계/개발 및 상호 인터페이스 확인을 위한 해석과 통합시험 등으로 완성된다. 여기서는 이와 같은 소형 가스터빈 엔진을 이용한 유도탄 추진시스템 체계통합기술의 구성과 각 단계별 요소기술의 개요를 서술한다.

• 한국전자파학회지:전자파기술
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• 제24권2호
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• pp.23-34
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• 2013

Over the past several decades in the microelectronics industry, devices have gotten smaller, thinner, and lighter, without any accompanying degradation in quality, performance, and reliability. One permanent and deniable trend in packaging as well as wafer fabrication industry is system integration. The proliferating options for system integration, recently, are driving change across the overall semiconductor industry, requiring more investment in developing, ramping and supporting new die-, wafer- and board-level solution. The trend toward 3D system integration and miniaturization in a small form factor has accelerated even more with the introduction of smartphones and tablets. In this paper, the key issues and state of the art for system integration in the packaging process are introduced, especially, focusing on ease transition to next generation packaging technologies like through silicon via (TSV), 3D wafer-level fan-out (WLFO), and chip-on-chip interconnection. In addition, effective solutions like fine pitch copper pillar and MEMS packaing of both advanced and legacy products are described with several examples.

• 한국정밀공학회지
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• 제18권4호
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• pp.129-134
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• 2001

It is essential to predict the welding deformation at assembly stage, to increase productivity through mechanization and automation effectively. A practical analysis method appled for production engineering was proposed to simulate the deformation of arc welding, with an analytical model using finite element method solving thermal-elastic-plastic behavior. In this research, for accurate assembling, 3-D thermal-elastic-plastic finite element model is used to simulate the out-of-plane deformation caused by arc welding. Efforts have been made to find out the efficient method to improve the reliability and accuracy of the numerical calculation. Each of theories of small and large deformation is applied in solving 3-D thermal-elastic-plastic problem to compare with their efficiency about calculation imes and solution accuracy. When solid elements are used in a bending problem of a plate, phenomenon that the predictive deformation is more than that of actual survey is observed. To prevent this phenomenon, reduced integration method for element is employed instead of full integration that is generally used in 3-D thermal-elastic-plastic analysis.

• 한국전자파학회지:전자파기술
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• 제24권2호
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• pp.51-57
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• 2013

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.