• Korean Journal of Computational Design and Engineering
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• v.11 no.6
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• pp.429-439
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• 2006

The purpose of this study is to support the integration from current 2D drawing-based design to future 3D model-based design. In this paper, an important theme is the combination between the STEP-based 2D drawing standards (i.e., AP202) and the IFC-based 3D building model standards. To achieve the purpose, two methodologies are proposed as follows: the development of IFC extension model for the 2D shape data representation by harmonizing ISO/STEP AP202; and the development of mapping solution between IFC 2D extension model and KOSDIC by constructing the exchange scenario for 2D shape data representation. It is expected that the proposed IFC2X2 2D extension model and mapping solution will offer the basis of development of the integrated standards model in AEC industry.

• ETRI Journal
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• v.34 no.5
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• pp.706-712
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• 2012

In previous work, novel maskless bumping and no-flow underfill technologies for three-dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low-volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no-flow underfill material named "fluxing underfill" is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two-tier stacked TSV chips are sucessfully stacked.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.203-207
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• 1999

In this paper we report new integration technology developed for three-dimensional metallic microstructures in an arbitrary shape. We have developed the two fabrication methods: Multi-Exposure and Single-Development (MESD) and Sacrificial Metallic Mold(SMM) techniques. Three-dimensional photoresist mold can be formed by the MESD method while unlimited number of structural levels can be realized by the SMM technique. Using these two techniques we have fabricated solenoid inductors and levitated spiral inductors for RF applications. We have achieved peak Q- factors over 40 in the 2-10㎓ range, the highest number among the inductors reported to date. Finally, we propose "On-Chip Passives" as a post IC process for monolithic integration of inductors, tunable capacitors, microwave switches, transmission lines, and mixers and filters toward future single-chip transceiver integration.

• Journal of Korea Multimedia Society
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• v.21 no.8
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• pp.1021-1026
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• 2018

3D SCAN enables easy human body measurement via a digital method in the process of film costume production which used to be done manually. Software-oriented computer graphic, which integrates 3D SCAN data in the process of manual film costume production, can induce quick and diverse design outcomes. While, 3D PRINT, which integrates computer graphic data in the process of manual film costume production, can automate the process of special costume production using a digital method. Integration of 3D Scan + Computer Graphic + 3D Print using integrated platforms for tailored costume production as developed in this study allows significant reduction of costume production period and costs. It also allows efficient integration of costume production outcomes in various industries related with OSMU contents in particular. In other words, using it, we can create a new business market that integrates multiple areas of film content, drama content and game content.

• Korean Journal of Computational Design and Engineering
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• v.20 no.2
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• pp.145-158
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• 2015

ISO 15926 is an international standard for the sharing and integration of plant lifecycle information. Plant design data consist of logical configuration, equipment specifications, 2D piping and instrument diagrams (P&IDs), and 3D plant models (shape data). Although 3D computer-aided design (CAD) data is very important data across the plant lifecycle, few studies on the exchange of 3D CAD data using ISO 15926 have been conducted so far. For this, we analyze information requirements regarding plant 3D design in the process industry. Based on the analysis, ISO 15926 templates are defined for the representation of constructive solid geometry (CSG) - based 3D design data. Since system environments for 3D CAD modeling and Semantic Web technologies are different from each other, we present system architecture for processing and visualizing plant 3D design data in the Web Ontology Language (OWL) format. Through the visualization test of ISO 15926-based 3D design data for equipment with a prototype system, feasibility of the proposed method is verified.

• Proceedings of the Korea Contents Association Conference
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• 2007.11a
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• pp.530-534
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• 2007

Flow visualization is one of visualization techniques and it means a visual expression of vector data using 2D or 3D graphics. It aims for human to easily understand a special feature of the vector data. Flow visualization can be classified into various criterions such as visualization technique, data dimension, type of the flow, and so on. Visualization technique can be categorized into direct method, integration method and derived data based method. Data dimension can be divided into 2D, 2.5D and 3D. Type of flow data may be classified into steady and unsteady. In this paper, various LIC based flow visualization methods will be introduced which is one of representative integration based techniques. Those methods will be categorized with more detailed criterions such as dimension and type of flows.

• Journal of the Korean Society of Propulsion Engineers
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• v.25 no.3
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• pp.81-88
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• 2021

An airbreathing propulsion system of a subsonic cruise missile is mainly composed of a small gas turbine engine, air intake and vehicle's fuel tank. The propulsion system integration work started from engine acceptance test is finally closed by ground functional test of the missile's propulsion section, after some modifications of engine's sub-components, development of engine-related onboard systems, interface analyses, and tests. The whole process and stepwise technologies of this system integration work are described herein.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.23-34
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• 2013

Over the past several decades in the microelectronics industry, devices have gotten smaller, thinner, and lighter, without any accompanying degradation in quality, performance, and reliability. One permanent and deniable trend in packaging as well as wafer fabrication industry is system integration. The proliferating options for system integration, recently, are driving change across the overall semiconductor industry, requiring more investment in developing, ramping and supporting new die-, wafer- and board-level solution. The trend toward 3D system integration and miniaturization in a small form factor has accelerated even more with the introduction of smartphones and tablets. In this paper, the key issues and state of the art for system integration in the packaging process are introduced, especially, focusing on ease transition to next generation packaging technologies like through silicon via (TSV), 3D wafer-level fan-out (WLFO), and chip-on-chip interconnection. In addition, effective solutions like fine pitch copper pillar and MEMS packaing of both advanced and legacy products are described with several examples.

• Journal of the Korean Society for Precision Engineering
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• v.18 no.4
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• pp.129-134
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• 2001

It is essential to predict the welding deformation at assembly stage, to increase productivity through mechanization and automation effectively. A practical analysis method appled for production engineering was proposed to simulate the deformation of arc welding, with an analytical model using finite element method solving thermal-elastic-plastic behavior. In this research, for accurate assembling, 3-D thermal-elastic-plastic finite element model is used to simulate the out-of-plane deformation caused by arc welding. Efforts have been made to find out the efficient method to improve the reliability and accuracy of the numerical calculation. Each of theories of small and large deformation is applied in solving 3-D thermal-elastic-plastic problem to compare with their efficiency about calculation imes and solution accuracy. When solid elements are used in a bending problem of a plate, phenomenon that the predictive deformation is more than that of actual survey is observed. To prevent this phenomenon, reduced integration method for element is employed instead of full integration that is generally used in 3-D thermal-elastic-plastic analysis.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.51-57
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• 2013

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.