• 제목/요약/키워드: 3D integrated circuits

검색결과 107건 처리시간 0.021초

CPW 구조를 이용한 94 GHz Branch-line 대역통과 여파기의 설계 및 제작 (Design and Fabrication of the 94 GHz Branch-line Bandpass Filter using CPW structure)

  • 권혁자;방석호;이상진;윤진섭;이진구
    • 대한전자공학회논문지SD
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    • 제44권5호
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    • pp.36-41
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    • 2007
  • 본 논문에서는 밀리미터파 대역에서 동작하는 단일 평면 구조의 회로에 쉽게 집적화 할 수 있는 94 GHz CPW branch-line 대역통과 여파기를 설계 및 제작하였다. 본 논문은 커플링 포트들을 open load stub로 연결하고, 격리 포트를 출력노드로 취하여 branch-line 커플러를 transversal filtering section으로 사용하는 것이다. 94 GHz branch-line 대역통과 여파기를 설계하기 위해서 CPW 라이브러리를 구축하고, branch-line 커플러와 open load stub들의 임피던스 및 길이를 최적화하였다. 제작된 대역통과 여파기의 측정결과, 주파수 94 GHz를 중심으로 11.7 %의 3 dB 상대 대역폭과 2.5 dB의 삽입 손실 특성을 나타내었다. 또한, 94 GHz에서 -18.5 dB의 입출력 반사 손실 특성을 얻었다.

레이더용 X-대역 63 Watt Pulsed SSPA 개발 (A Development of the X-Band 63 Watt Pulsed SSPA for Radar)

  • 정민길;나형기
    • 한국전자파학회논문지
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    • 제22권3호
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    • pp.380-388
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    • 2011
  • 본 논문에서는 소형 하이브리드 HMIC(Hybrid Microwave Integrated Circuits)를 사용하여 레이더용 X-대역 63 watt 펄스 구동형(pulsed) SSPA(Solid State Power Amplifier)를 개발하였다. Pulsed SSPA는 전원공급기와 초단증폭기, 구동증폭기, 고출력을 위한 최종단 증폭기의 3단의 증폭기로 구성되어 있다. 70도의 고온에서도 듀티 1.2%이고, 짧은 펄스 폭에서 63 watts 이상의 출력을 얻었다. 제작된 모듈은 동작대역 내에서 포화 상태의 이득 37 dB 성능을 보였다. 입출력 정재파비는 1.5:1 미만을 만족하였다. 이 모듈은 +28 $V_{dc}$로 동작되고 400 mA 전력 소모를 가진다. 본 논문에서 개발한 SSPA는 고속으로 동작하는 펄스 도플러 레이더에 적용할 수 있다.

저온 동시소성 공정으로 제작된 3차원 매립 인덕터 모델링 (Modeling of 3-D Embedded Inductors Fabricated in LTCC Process)

  • 이서구;최종성;윤일구
    • 한국전기전자재료학회논문지
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    • 제15권4호
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    • pp.344-348
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    • 2002
  • As microelectronics technology continues to progress, there is also a continuous demand on highly integration and miniaturization of systems. For example, it is desirable to package several integrated circuits together in multilayer structure, such as multichip modules, to achieve higher levels of compactness and higher performance. Passive components (i.e., capacitors, resistors, and inductors) are very important fort many MCM applications. In addition, the low-temperature co-fired ceramic (LTCC) process has considerable potential for embedding passive components in a small area at a low cost. In this paper, we investigate a method of statistically modeling integrated passive devices from just a small number of test structures. A set of LTCC inductors is fabricated and their scattering parameters (s-parameters) are measured for a range of frequencies from 50MHz to 5GHz. An accurate model for each test structure is obtained by using a building block based modeling methodology and circuit parameter optimization using the HSPICE circuit simulator.

원전용 IC를 위한 CMOS 디지털 논리회로의 내방사선 모델 설계 및 누적방사선 손상 분석 (A Radiation-hardened Model Design of CMOS Digital Logic Circuit for Nuclear Power Plant IC and its Total Radiation Damage Analysis)

  • 이민웅;이남호;김종열;조성익
    • 전기학회논문지
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    • 제67권6호
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    • pp.745-752
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    • 2018
  • ICs(Integrated circuits) for nuclear power plant exposed to radiation environment occur malfunctions and data errors by the TID(Total ionizing dose) effects among radiation-damage phenomenons. In order to protect ICs from the TID effects, this paper proposes a radiation-hardening of the logic circuit(D-latch) which used for the data synchronization and the clock division in the ICs design. The radiation-hardening technology in the logic device(NAND) that constitutes the proposed RH(Radiation-hardened) D-latch is structurally more advantageous than the conventional technologies in that it keeps the device characteristics of the commercial process. Because of this, the unit cell based design of the RH logic device is possible, which makes it easier to design RH ICs, including digital logic circuits, and reduce the time and cost required in RH circuit design. In this paper, we design and modeling the structure of RH D-latch based on commercial $0.35{\mu}m$ CMOS process using Silvaco's TCAD 3D tool. As a result of verifying the radiation characteristics by applying the radiation-damage M&S (Modeling&Simulation) technique, we have confirmed the radiation-damage of the standard D-latch and the RH performance of the proposed D-latch by the TID effects.

KaBand 3단 MMIC 저잡음 증폭기 설계 (Design of Ka-Band 3 Stage MMIC Low Noise Amplifiers)

  • 염인복;정진철;이성팔
    • 한국전자파학회:학술대회논문집
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    • 한국전자파학회 2000년도 종합학술발표회 논문집 Vol.10 No.1
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    • pp.216-219
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    • 2000
  • A Ka Band 3-stage MMIC (Monolithic Microwave Integrated Circuits) LNA(Low Noise Amplifiers) has been designed. The MMIC LNA consists of two single-ended type amplication stapes and one balanced type amplication stage to satisfy noise figure characteristics and high gain and amplitude linearity. The 0.15um pHEMT has been used to provide a ultra low noise figure and high gain amplification. Series and Shunt feedback circuits were inserted to ensure high stability over frequency range of DC to 80 GHz. The size of designed MMIC LNA is 3100mm ${\times}$ 2400um(7.44$\textrm{mm}^2$). The on wafer measured noise figure of the MMIC LNA is less than 2.0 dB over frequency range of 22 GHz to 30 GHz.

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LTCC 공정을 이용한 K/Ka 대역에서의 송수신 겸용 L 형태 원형편파 안테나 (Design of TX/RX broadband L-type circular polarization Antenna using LTCC at K/Kaband)

  • 오민석;천영민;김성남;최재익;표철식;이종문;천창율
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2004년도 하계학술대회 논문집 C
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    • pp.2052-2054
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    • 2004
  • The TX/RX broadband L-type circular polarization antenna using LTCC at K/Ka band has been presented. This antenna has been analyzed in compensation for LTCC with relative permittivity 5.2 and could have been integrated with RF component. As the measured 10dB impedance circular polarization bandwidth of the proposed antenna is 7%(20.8GHz${\sim}$22.2GHz) at the K band and 2.3%(30.9GHz to 31.6GHz) at the Ka band. Also the gain of the antenna is -0.7${\sim}$3.05dBi at the K band and -2.8${\sim}$1dBi at the Ka band. The purpose of the research is to design an efficient antenna structure for satellite communication at K/Ka band. the antenna should be used for both TX and RX frequency bands. The antenna will be mounted on LTCC(Low Temperature Co-fired Ceramic) so that it can be integrated with other RF circuits. This research is important because of the following reasons. 1) The frequency ranges of satellite communication tends to move up to higher frequency such as Ka band or milimeter wave band. 2) Design of antenna for smaller size, lighter weight and less loss is preferred by most RF engineers. 3) Antennas on LTCC enables to integrate the antenna with other RF circuits, and thus, one can reduce the size and loss of the RF system.

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나노선 기반 논리 회로의 이차원 시뮬레이션 연구 (Two-dimensional numerical simulation study on the nanowire-based logic circuits)

  • 최창용;조원주;정홍배;구상모
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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    • pp.82-82
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    • 2008
  • One-dimensional (1D) nanowires have been received much attention due to their potential for applications in various field. Recently some logic applications fabricated on various nanowires, such as ZnO, CdS, Si, are reported. These logic circuits, which consist of two- or three field effect transistors(FETs), are basic components of computation machine such as central process unit (CPU). FETs fabricated on nanowire generally have surrounded shapes of gate structure, which improve the device performance. Highly integrated circuits can also be achieved by fabricating on nano-scaled nanowires. But the numerical and SPICE simulation about the logic circuitry have never been reported and analyses of detailed parameters related to performance, such as channel doping, gate shapes, souce/drain contact and etc., were strongly needed. In our study, NAND and NOT logic circuits were simulated and characterized using 2- and 3-dimensional numerical simulation (SILVACO ATLAS) and built-in spice module(mixed mode).

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Optimal pressure and temperature for Cu-Cu direct bonding in three-dimensional packaging of stacked integrated circuits

  • Seunghyun Yum;June Won Hyun
    • 한국표면공학회지
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    • 제56권3호
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    • pp.180-184
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    • 2023
  • Scholars have proposed wafer-level bonding and three-dimensional (3D) stacked integrated circuit (IC) and have investigated Cu-Cu bonding to overcome the limitation of Moore's law. However, information about quantitative Cu-Cu direct-bonding conditions, such as temperature, pressure, and interfacial adhesion energy, is scant. This study determines the optimal temperature and pressure for Cu-Cu bonding by varying the bonding temperature to 100, 150, 200, 250, and 350 ℃ and pressure to 2,303 and 3,087 N/cm2. Various conditions and methods for surface treatment were performed to prevent oxidation of the surface of the sample and remove organic compounds in Cu direct bonding as variables of temperature and pressure. EDX experiments were conducted to confirm chemical information on the bonding characteristics between the substrate and Cu to confirm the bonding mechanism between the substrate and Cu. In addition, after the combination with the change of temperature and pressure variables, UTM measurement was performed to investigate the bond force between the substrate and Cu, and it was confirmed that the bond force increased proportionally as the temperature and pressure increased.

DSRC 송신기를 위한 능동발룬 내장형 5.8 GHz SiGe 상향믹서 설계 및 제작 (A 5.8 GHz SiGe Up-Conversion Mixer with On-Chip Active Baluns for DSRC Transmitter)

  • 이상흥;이자열;김상훈;배현철;강진영;김보우
    • 한국통신학회논문지
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    • 제30권4A호
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    • pp.350-357
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    • 2005
  • 근거리무선통신 (Dedicated Short Range Communication, DSRC)은 지능형교통시스템 서비스 제공을 위한 통신 수단으로, 수 미터에서 수백 미터인 근거리 영역의 노변장치(Road Side Equipment, RSE)와 차량탑재장치(On-Board Equipment, OBE)와의 양방향 고속통신을 수행하는 통신시스템이다. 본 논문에서는 SiGe HBT 공정을 이용하여 근거리무선통신 송신기용 5.8 GHz 상향믹서를 설계 및 제작하였다. 설계된 상향믹서는 믹서코어 회로와 더불어 IF/LO/RF 입출력 정합 회로, IF/LO 입력 발룬 회로와 RF 출력 발룬 회로가 단일칩으로 구현되었다. 제작된 상향믹서는 $2.7 mm\times1.6mm$의 크기를 가지며, 3.5 dB의 전력변환이득과 -12.5 dBm의 OIP3, 42 dB의 LO to E isolation, 38 dB의 LO to RF isolation, 3.0 V의 공급전압 하에서 29 mA의 전류소모로 측정되었다.

Ku-Band Power Amplifier MMIC Chipset with On-Chip Active Gate Bias Circuit

  • Noh, Youn-Sub;Chang, Dong-Pil;Yom, In-Bok
    • ETRI Journal
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    • 제31권3호
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    • pp.247-253
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    • 2009
  • We propose a Ku-band driver and high-power amplifier monolithic microwave integrated circuits (MMICs) employing a compensating gate bias circuit using a commercial 0.5 ${\mu}m$ GaAs pHEMT technology. The integrated gate bias circuit provides compensation for the threshold voltage and temperature variations as well as independence of the supply voltage variations. A fabricated two-stage Ku-band driver amplifier MMIC exhibits a typical output power of 30.5 dBm and power-added efficiency (PAE) of 37% over a 13.5 GHz to 15.0 GHz frequency band, while a fabricated three-stage Ku-band high-power amplifier MMIC exhibits a maximum saturated output power of 39.25 dBm (8.4 W) and PAE of 22.7% at 14.5 GHz.

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