• 한국광학회지
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• 제20권4호
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• pp.211-216
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• 2009

초소형 광집적 회로를 실현하기 위해 실리콘 기반의 2차원 광자 결정에 대한 연구가 활발히 이루어지고 있다. 그 중에서 대표적 구조인 공기 클래딩을 갖는 2차원 실리콘 광자 결정은 우수한 광학적 특성을 가지나, 다양한 소자를 집적화하기에는 기계적 강도가 약하다. 본 연구에서는 기계적 강도를 향상시킨 대칭적인 저굴절률 실리카 클래딩을 갖는 2차원 실리콘 광자 결정을 제안하며, 공기 및 실리카 클래딩을 갖는 광자 결정 슬랩 구조의 광학적 특성을 이론적으로 비교하였다. 3차원 유한 차분 시간 영역법을 이용하여 공기 클래딩을 갖는 2차원 실리콘 광자 결정 슬랩 구조를 분석한 결과, 광통신 대역에서 약 330 nm의 광자 밴드갭과 약 100 nm의 무손실 도파 대역을 가짐을 보였다. 이러한 결과를 바탕으로 실리카 클래딩을 갖는 2차원 광자 결정 슬랩 구조를 계산한 결과, 클래딩의 굴절률이 공기보다 높음에도 불구하고 공기 클래딩 구조의 광학적 특성에 버금가는 약 230 nm의 광자 밴드갭과 약 90 nm의 무손실 도파 대역을 갖는 구조를 설계하였다.

• 전자공학회논문지SC
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• 제42권5호
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• pp.43-50
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• 2005

본 논문에서는 체성분 측정기용 저 전력 다중 대역을 가지는 Gm-C 대역통과 필터의 IC화 설계방법에 대해 기술하였다. 제안된 대역통과 필터는 제어 신호에 의해 3개의 중심 주파수(20 KHz, 50 KHz, 100 KHz)에서 동작한다. 칩 면적을 최소화하기 위해 간단한 주파수 튜닝회로가 사용되었으며 전력 소모를 줄이기 위해 OTA(operational transconductance amplifier)가 sub-threshold region에서 동작한다. 제안된 대역통과 필터는 0.35 um 2-poly 3-metal 표준 CMOS 공정을 이용하여 구현하였다. 칩 면적은 $626.42um\;{\times}\;475.8um$이며 전력 소모는 주파수가 100 KHz일 때 700 nW이다.

• 한국광학회지
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• 제17권5호
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• pp.469-474
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• 2006

본 논문에서는 실리카 기반의 다중모드 간섭기를 이용하여 적은 초과손실을 갖는 $1{\times}16$ 마하젠더 스위치에 대한 설계 및 측정결과에 대하여 논하였다. 제작된 $1{\times}16$ 마하젠더 스위치는 마하젠더 간섭계(Mach-Zehnder Interferometer, MZI) 구조를 갖는 $2{\times}2$ 열광학스위치를 단위소자로 하였으며, 15개의 단위소자를 이용하여 4단(stage)으로 구성하였다. 먼저 광분배기와 $2{\times}2$ MZI 열광학 스위치등의 개별적인 특성을 파악하였고, 그 결과를 전체 소자의 설계에 적용함으로써 보다 좋은 성능을 얻을 수 있었다. 제작된 다중모드 간섭기를 이용한 MZI 구조의 단위스위치 당 초과손실은 최소 -0.5dB로 측정되었다.

• 한국근적외분광분석학회:학술대회논문집
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• 한국근적외분광분석학회 2001년도 NIR-2001
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• pp.2101-2101
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• 2001

Near-infrared spectroscopy is now being used in clinical diagnosis as a non-invasive monitor of tissue oxygenation state. However, due to lack of the optical pathlength information within tissues, it is still difficult to quantitate the hemoglobin concentration with present CW techniques. Time-resolved spectroscopy (TRS), which measures temporal profiles of emerging light from tissues, enables to estimate the pathlength distribution within tissues by converting time to distance. Consequently, quantitative measurement of tissue oxygenation is possible by analyzing the data with optical diffusion equation 1) or our Microscopic Beer-Lambert law2). Time-Resolved Spectroscopy System : TRS-1O3) Our TRS-10 system consists of a three-wavelength (759, 797, 833 nm) PLP as pulsed light source, a high speed PMT with high sensitivity and three signal-processing circuits for time-resolved measurement (CFD/TAC, A/D converter and histogram memory). Optical pulse train consisting of 759, 797 and 833nm is generated by PLP at 5㎒ repetition rate and irradiated a sample through a single optical fiber. The diffuse-reflected light from the sample is collected by a bundle fiber and then detected by the PMT for single photon measurement. After being amplified by a following fast amplifier, the electrical signals for each wavelength are picked out by CFD/TAC module. Then, a signal processing circuit integrated the TRS data for each wavelength individually. The simultaneous TRS measurement for three wavelengths achieved without any optical or mechanical switch. Experiment and Results Input and detection fibers of TRS-10 were attached at the human forehead with a fiber separation of 3cm. TRS measurements were continuously performed for about 20 minutes including 2 minutes hyper ventilation. It was observed that the total hemoglobin concentration was decreasing during the hyper ventilation and recovered until 2 minutes after hyper ventilation. On the other hand, the deoxy-hemoglobin concentration began to increase after hyper ventilation and had its peak at around 2 minute later, showing 502 drop from 75% to 60% due to inhibition of breathing by performing hyper ventilation. The results showed that this system might be able to quantitate the concentrations of oxy- and deoxy-hemoglobin in the human brain.

• 한국정보통신학회논문지
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• 제9권2호
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• pp.301-306
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• 2005

본 논문에서는 gain-boosting 회로를 이용하여 전류 미스매치를 줄일 수 있는 전하펌프와 전압제어 저항기를 사용하여 선형성이 우수한 래치 구조의 전압제어발생기를 제안하여 위상고정루프를 설계하였다. Cain-boosting 전하펌프를 사용한 위상고정루프는 루프필터 출력 전압 구간에서 11$mu$V(최대 43$mu$V, 최소 32$mu$V)의 전압 흔들림 차이를 나타내었다. 전압제어저항기를 이용한 전압제어발진기는 입력전압 동작 구간에서 우수한 선형성을 나타내었다. 또한 제작된 전압제어발진기의 위상 잡음 특성은 -1084Bc/Hz(a)100kHz이며 CMOS 공정으로 만들어진 LC 전압제어발진기와 비슷한 성능을 가진다. 0.35$mu$m CMOS 공정으로 시뮬레이션 하였으며 록킹 시간은 150$mu$s이다.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}