• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.39 no.2
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• pp.73-79
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• 2021

Recently there are growing interests on the energy conservation and emission reduction. In the fields of architecture and civil engineering, the energy monitoring of structures is required to response the energy issues. In perspective of thermal monitoring, thermal images gains popularity for their rich visual information. With the rapid development of the drone platform, aerial thermal images acquired using drone can be used to monitor not only a part of structure, but wider coverage. In addition, the stereo photogrammetric process is expected to generate 3D point cloud with thermal information. However thermal images show very poor in resolution with narrow field of view that limit the use of drone-based thermal photogrammety. In the study, we aimed to generate 3D thermal point cloud using visible and thermal images. The visible images show high spatial resolution being able to generate precise and dense point clouds. Then we extract thermal information from thermal images to assign them onto the point clouds by precisely establishing photogrammetric collinearity between the point clouds and thermal images. From the experiment, we successfully generate dense 3D thermal point cloud showing 3D thermal distribution over the building structure.

• Journal of Ship and Ocean Technology
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• v.12 no.3
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• pp.1-13
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• 2008

In shipbuilding, diverse manufacturing techniques for automation have been developed and used in practice. Among them, however, the hull forming automation is the one that has not been of major concern compared with others such as welding and cutting. The basis of the development of this process is to find out how to extract thermal forming information. There exist various methods to obtain such information and the 3D design shape that needs to be formed should be extracted first for getting the necessary thermal forming information. Except well-established shipyards which operate 3D design systems, most of the shipyards only rely on 2.5D design systems and do not have an easy way to obtain 3D surface design data. So in this study, various shipbuilding design systems used by shipyards are investigated and a 3D design surface data extraction method is proposed from those design systems. Then an example is presented to show the extraction of real 3D surface data using the proposed method and computation of thermal forming information using the data.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.103-110
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• 2014

Recent TSV based 3D Integrated Circuit (IC) technology needs more powerful thermal management techniques. However, because cooling cost and form factor are restricted, thermal management are emphasis on software based techniques. But in case of throttling thermal management which one of the most candidate technique, increasing bus occupation induce total performance decrease. To solve communication bottleneck issue in TSV based 3D SoC, we proposed adaptive throttling technique Experimental results show that the proposed method can improve throughput by about 72% compare with minimal path routing.

• Elastomers and Composites
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• v.52 no.3
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• pp.216-223
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• 2017

The additive manufacturing technology, also called 3D printing, is growing fast. There are several methods for 3D printing. Fused deposition modeling (FDM) type 3D printing is the most popular method because it is simple and inexpensive. Moreover, it can be used for printing various thermoplastic materials. However, it contains the cooling of layered road and causes thermal shrinkage. Thermal shrinkage should be controlled to obtain high-quality products. In this study, temperature distribution and cooling behavior of a layered road with cooling are studied through computer simulation. The thermal shrinkage of the layered road was simulated using the calculated temperature distribution with time. Shape variation of the layered road was predicted as cooling proceeded. Stress between the bed and the layered road was also predicted.This stress was considered as the detaching stress of the layered road from the bed. The simulations were performed for various thermal conductivities and temperatures of the layered road, bed temperature, and chamber temperature of a 3D printer. The simulation results provide detailed information about the layered road for FDM type 3D printing under operational conditions.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.297-312
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• 2012

For future multi-core processors, 3D integration is regarded as one of the most promising techniques since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems since the closer proximity of heat generating dies makes existing thermal hotspots more severe. Conventional air cooling schemes are not enough for 3D multi-core processors due to the limit of the heat dissipation capability. Without more efficient cooling methods such as liquid cooling, the performance of 3D multi-core processors should be degraded by dynamic thermal management. In this paper, we examine the architectural impact of cooling methods on the 3D multi-core processor to find potential benefits of liquid cooling. We first investigate the thermal behavior and compare the performance of two different cooling schemes. We also evaluate the leakage power consumption and lifetime reliability depending on the temperature in the 3D multi-core processor.

• Journal of the Korea Society of Computer and Information
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• v.15 no.11
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• pp.1-9
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• 2010

As the process technology scales down, an interconnection has became a major performance constraint for multi-core processors. Recently, in order to mitigate the performance bottleneck of the interconnection for multi-core processors, a 3D integration technique has drawn quite attention. The 3D integrated multi-core processor has advantage for reducing global wire length, resulting in a performance improvement. However, it causes serious thermal problems due to increased power density. For this reason, to design efficient 3D multi-core processors, thermal-aware design techniques should be considered. In this paper, we analyze the temperature on the 3D multi-core processors in function unit level through various experiments. We also present temperature characteristics by varying application features, cooling characteristics, and frequency levels on 3D multi-core processors. According to our experimental results, following two rules should be obeyed for thermal-aware 3D processor design. First, to optimize the thermal profile of cores, the core with higher cooling efficiency should be clocked at a higher frequency. Second, to lower the temperature of cores, a workload with higher thermal impact should be assigned to the core with higher cooling efficiency.

• Computers and Concrete
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• v.18 no.3
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• pp.319-336
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• 2016

In this study, both two- and three-dimensional (2D and 3D) finite-volume-based models were developed to analyze the heat transfer mechanisms through the porous structures of cellular concretes under steady-state heat transfer conditions and to investigate the differences between the 2D and 3D modeling results. The 2D and 3D reconstructed pore networks were generated from the microstructural information measured by 3D images captured by X-ray computerized tomography (X-CT). The computed effective thermal conductivities based on the 2D and 3D calculations performed on the reconstructed porous structures were found to be nearly identical to those evaluated from the 2D cross-sectional images and the 3D X-CT images, respectively. In addition, the 3D computed effective thermal conductivity was found to agree better with the measured values, in comparison with the 2D reconstruction and real cross-sectional images. Finally, the thermal conductivities computed for different reconstructed porous 3D structures of cellular concretes were compared with those obtained from 2D computations performed on 2D reconstructed structures. This comparison revealed the differences between 2D and 3D image-based modeling. A correlation was thus derived between the results of the 3D and 2D models.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2085-2098
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• 2016

Laminated busbars with a low stray inductance are widely used in NPC three-level inverters, even though some of them have poor performances in heat equilibrium and overvoltage suppression. Therefore, a theoretical method is in need to establish an accurate mathematical model of laminated busbars and to calculate the impedance and stray inductance of each commutation loop to improve the heat equilibrium and overvoltage suppression performance. Firstly, an equivalent circuit of a NPC three-level inverter laminated busbar was built with an analysis of the commutation processes. Secondly, on the basis of a 3D (three dimensional) cubical thermal model and mirror circulation theory, a supersymmetric mirror circulation 3D cubical thermal model was built. Based on this, the laminated busbar was decomposed in 3D space to calculate the equivalent resistance and stray inductance in each commutation loop. Finally, the model and analysis results were put into a busbar design, simulation and experiments, whose results demonstrate the accuracy and feasibility of the proposed method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.187-191
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• 2007

This paper describes a 3.3V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method with monotonicity, glitch energy. The output stage utilizes here implements a return-to-zero circuit to obtain the dynamic performance. Most of D/A converters in decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. the designed D/A converter using the CMOS n-well $0.35{\mu}m$ process0. The experimental data shows that the rise/fall time, settling time, and INL/DNL are 1.90ns/2.0ns, 12.79ns, and a less than ${\pm}2.5/{\pm}0.7$ LSB, respectively. The power dissipation of the D/A converter with a single power supply of 3.3V is about 250mW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.4
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• pp.691-698
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• 2008

This paper describes a 3.3V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method with monotonicity, glitch energy. The output stage utilizes here implements a return-to-zero circuit to obtain the dynamic performance. Most of D/A converters in decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. the designed D/A converter using the CMOS n-well $0.35{\mu}m$ process0. The experimental data shows that the rise/fall time, settling time, and INL/DNL are 1.90ns/2.0ns, 12.79ns, and a less than ${\pm}2.5/{\pm}0.7\;LSB$, respectively. The power dissipation of the D/A converter with a single power supply of 3.3V is about 250mW.