• Journal of Digital Contents Society
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• v.6 no.3
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• pp.169-174
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• 2005

In this paper we propose efficient design and implementation of JPEG image display board that can display JPEG image on TV. we used NAND Flash Memory to save the compressed JPEG bit stream and video encoder to display the decoded JPEG mage on TV. Also we convert YCbCr to RGB to super impose character on JPEG image. The designed B/D is implemented using FPGA.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.260-264
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• 2017

Process variation effect on arch-structured gate stacked array (GSTAR) 3-D NAND flash is investigated. In case of arch-structured GSTAR, a shape of the arch channel is depending on an alignment of photo-lithography. Channel width fluctuates according to the channel hole alignment. When a shape of channel exceeds semicircle, channel width becomes longer, increasing drain current. However, electric field concentration on tunnel oxide decreases because less electric flux converges into a larger surface of tunnel oxide. Therefore, program efficiency is dependent on the process variation. Meanwhile, a radius of channel holes near the bottom side become smaller due to an etch slope. It also affects program efficiency as well as channel width. Larger hole radius has an advantage of higher drain current, but causes degradation of program speed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.5
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• pp.452-458
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• 2022

The electro-thermal erasing (ETE) configuration utilizes Joule heating intentionally generated at word-line (WL). The elevated temperature by heat physically removes stored electrons permanently within a very short time. Though the ETE configuration is a promising next generation NAND flash memory candidate, a consideration of power efficiency and erasing speed with respect to device structure and its scaling has not yet been demonstrated. In this context, based on 3-dimensional (3-D) thermal simulations, this paper discusses the impact of device structure and scaling on ETE efficiency. The results are used to produce guidelines for ETEs that will have lower power consumption and faster speed.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.4
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• pp.35-39
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• 2019

The shielding effectiveness (SE) of the EMI spray coating film was measured in a three-dimensional structure. The shielding effectiveness was measured by AST D4935 using coaxial type TEM cell. A standard sample of the cylindrical slab is fabricated to measure the shielding effectiveness using the ASTM D4935. At this time, spray coating was performed by bonding a three-dimensional structure with NAND flash memory to a standard sample. In the case of spray coating, it was uniformly coated not only on the horizontal plane but also on the vertical plane of the three-dimensional structure. As a result of measurement, shielding effectiveness of maximum 59 dB was measured in a three-dimensional structure similar to the case without three-dimensional structure. As a result, it was confirmed that the spray coating can be uniformed even in the three-dimensional structure.

• Transactions on Electrical and Electronic Materials
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• v.16 no.4
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• pp.183-186
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• 2015

This research investigates the impact of charge spreading on the data retention of three-dimensional (3D) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory where the charge trapping layer is shared along the cell string. In order to do so, this study conducts an electrical analysis of the planar SONOS test pattern where the silicon nitride charge storage layer is not isolated but extends beyond the gate electrode. Experimental results from the test pattern show larger retention loss in the devices with extended storage layers compared to isolated devices. This retention degradation is thought to be the result of an additional charge spreading through the extended silicon nitride layer along the width of the memory cell, which should be improved for the successful 3-D application of SONOS flash devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.331-331
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• 2012

With the NAND Flash scaling down, it becomes more and more difficult to follow Moore's law to continue the scaling due to physical limitations. Recently, three-dimensional (3D) flash memories have introduced as an ideal solution for ultra-high-density data storage. In 3D flash memory, as the process reason, we need to use poly-Si TFTs instead of conventional transistors. So, after combining charge trap flash (CTF) structure and poly-Si TFTs, the emerging device SONOS-TFTs has also suffered from some reliability problem such as hot carrier degradation, charge-trapping-induced parasitic capacitance and resistance which both create interface traps. Charge pumping method is a useful tool to investigate the degradation phenomenon related to interface trap creation. However, the curves for charge pumping current in SONOS TFTs were far from ideal, which previously due to the fabrication process or some unknown traps. It needs an optimization and the important geometrical effect should be eliminated. In spite of its importance, it is still not deeply studied. In our work, base-level sweep model was applied in SONOS TFTs, and the nonideal charge pumping current was optimized by adjusting the gate pulse transition time. As a result, after the optimizing, an improved charge pumping current curve is obtained.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.360-369
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• 2012

The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

• Proceedings of the Korea Information Processing Society Conference
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• 2021.11a
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• pp.43-46
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• 2021

다양한 응용에서 저장 매체로 사용되는 NAND 플래시 메모리는 저비용과 대용량을 위해 셀 당 비트 수 증가, 제조 공정의 미세화, 그리고 적층 기술 등 다양한 기술을 사용한다. 그렇지만 이러한 기술들은 플래시 메모리 셀의 안정성과 성능에 악영향을 준다. 특히 QLC 3D 플래시 메모리인 경우, 셀 상태가 많고 상태 간 임계 전압 간격이 좁기 때문에 프로그램과 읽기에 필요한 시간이 길다. 본 논문에서는 프로그램 수행 시간을 줄이고 셀 안정성에 긍정적인 영향을 줄 수 있도록 데이터 코드를 변환하는 비균일 스크램블 기법을 소개하고, 실제 시스템 데이터를 이용하여 스크램블 기법의 성능을 평가한다. 시뮬레이션을 통해 얻은 결과에 따르면 데이터 코드를 변환하여 저장하는 스크램블 기법은 최대 204%의 프로그램 성능 개선 효과를 보인다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.877-880
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• 2005

As DMB, 3D game, Internet and movie is serviced for the recent mobile devices, high resolution display devices beyond VGA become used. Implementation of real-time moving pictures of 30렌 by software programming is difficult because the performance of mobile processors is not so high. The full frame moving picture can be supported by using specific hardware. In this paper, an OLED controller that is consists of flash memory controller and OLED interface is proposed for real-time moving picture on mobile displays. The proposed OLED controller is implemented in FPGA and the performance is evaluated.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.53-58
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• 2023

The storage capacity of 3D-NAND flash memory has been enhanced by the multi-layer dielectrics. The deposition process has become more challenging due to the tight process margin and the demand for accurate process control. To reduce product costs and ensure successful processes, process diagnosis techniques incorporating artificial intelligence (AI) have been adopted in semiconductor manufacturing. Recently there is a growing interest in process diagnosis, and numerous studies have been conducted in this field. For higher model accuracy, various process and sensor data are required, such as optical emission spectroscopy (OES), quadrupole mass spectrometer (QMS), and equipment control state. Among them, OES is usually used for plasma diagnostic. However, OES data can be distorted by viewport contamination, leading to misunderstandings in plasma diagnosis. This issue is particularly emphasized in multi-dielectric deposition processes, such as oxide and nitride (ON) stack. Thus, it is crucial to understand the potential misunderstandings related to OES data distortion due to viewport contamination. This paper explores the potential for misunderstanding OES data due to data distortion in the ON stack process. It suggests the possibility of excessively evaluating process drift through comparisons with a QMS. This understanding can be utilized to develop diagnostic models and identify the effects of viewport contamination in ON stack processes.