• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.275-280
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• 2006

We propose Doherty power amplifier structure which can be integrated in Silicon RF ICs. Doherty power amplifiers are widely used in RF transmitters, because of their high Power Added Efficiency (PAE) and good linearity. In this paper, it is proposed that a method to replace the quarter wavelength coupler with IQ up-conversion mixers to achieve 90 degree phase shift, which allows on-chip Doherty amplifier. This idea is implemented and manufactured in CMOS 5 GHz band direct-conversion RF transmitter. We measured a 3dB improvement output RF power and linearity.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.2
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• pp.165-170
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• 2016

Nano-scale power splitter based on curved plasmonic waveguides are designed by utilizing the multimode interference (MMI) coupler. To analyze easily the adaptive properties of plasmonic curverd multimode interference coupler(PC-MMIC), the curved form transforms equivalently into a planar form by using conformal transformation method. Also, effective dielectric method and longitudinal modal transmission-line theory are used for simulating the light propagation and optimizing the structural parameters at 3-D guiding geometry. The designed $2{\times}2$ PC-MMIC does not work well for quasi-TM mode case due to the bending structure, and it does not exist 3dB coupling property, in which the power splitting ratio is 50%:50%, for quasi-TE mode case. Further, the coupling efficiency is better when the signal is incident at channel with large curvature radius than small curvature radius.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.1
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• pp.199-205
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• 2015

Indoor positioning technology has been developed very actively for the smart phone handheld by most users. Especially, many TDOA positioning systems using acoustic signal have been studied, and it estimates the smart phone position by measuring the distance between the smart phone speaker and the microphones which is installed to receive the acoustic signal from the smart phone, and by calculating the hyperbolic equations. But there are always errors for the distance measurements, and furthermore the microphone installation error produces huge position estimation error. In this paper, the position estimation error due to the position error of acoustic sensor in the 3 dimensional TDOA positioning system, is analyzed by PDOP simulation and experiment.

• Journal of Chest Surgery
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• v.12 no.2
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• pp.119-126
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• 1979

This is one case report of the extremely rare congenital cardiac malformation, Double-outlet of left ventricle in corrected transposition of great arteries. 11-year-old boy complained acrocyanosis and exertional dyspnea, the parents noticed cyanosis since birth. Physical examination revealed acrocyanosis, clubbed fingers and toes, G-III pansystolic murmur on 2nd and 3rd ICS, LSB. Right heart catheterization revealed significant $O_2$ jump in ventricular level. Right and left ventriculography showed the both catheters arriving in the same ventricle i.e. anterior chamber, morphological left ventricle was in right and anterior position, simultaneous visualization of aorta and pulmonary artery and aorta locating anterior and right side of pulmonary artery. Echo cardiogram surely disclosed interventricular septum. Conclusively it was clarified that the patient has Double-outlet of left ventricle and corrected transposition of great arteries [S.L.D.]. Operation was performed to correct the anomalies under extracorporeal circulation with intermittent moderate hypothermia. Right-sided ventriculotomy disclosed the following findings. 1. Right-sided ventricle was morphological left ventricle. 2. Left-sided ventricle was morphological right ventricle. 3. Right side atrioventricular valve was bicuspid. 4. Left side atrioventricular valve was tricuspid. 5. Aortic valve was superior, anterior and right side of pulmonary valve. 6. Subpulmonary membranous stenosis. 7. Non-committed ventricular septal defect. We made a tunnel between VSD and aorta with Teflon patch so that arterial blood comes through VSD and the tunnel into aorta. After correction the patient needed assisted circulation for 135 min. to have adequate blood pressure. Postoperatively by any means, adequate blood pressure could not be maintained and expired in the evening of operation day.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.4
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• pp.171-177
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• 2013

Due to the demand for high speed 3D graphic rendering, video file format conversion, compression, encryption and decryption technologies, the importance of digital signal processor system is growing rapidly. In order to satisfy the real-time constraints, high performance digital signal processor is required. Therefore, as in general purpose computer systems, digital signal processor should be designed as multicore architecture as well. Using UTDSP benchmarks as input, the trace-driven simulation has been performed and analyzed for the 2 to 16-core digital signal processor architectures with the cores from simple RISC to in-order and out-of-order superscalar processors for the various window sizes, extensively.

• Journal of Biomedical Engineering Research
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• v.40 no.4
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• pp.132-136
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• 2019

This study proposes an auto-titrating algorithm for auto-titrating positive airway pressure (APAP). The process of the proposed algorithm is as follows. First, sleep apnea-hypopnea and snoring events were detected using nasal pressure. Second, APAP base pressure and SDB events were used for automatic titration of optimal pressure. And, auto-titrating algorithm is built into M3 (MEK-ICS CO. Ltd., Republic of Korea) for evaluation. The detection results of SDB showed mean sensitivity (Sen.) and positive predictive value (PPV.) of 85.7% and 87.8%, respectively. The mean pressure and apnea-hypopnea index (AHI) of auto-titrating algorithm showed $13.0{\pm}5.2cmH_2O$ and $3.0{\pm}2.4$ events/h, respectively. And, paired t-test was conducted to verify whether the performance of our algorithm has no significant difference with AutoSet S9 (p>0.05). These results represent better or comparable outcomes compared to those of previous APAP devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.129-140
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• 2017

In this paper, a $4{\times}32$-channel neural recording system capable of acquiring neural signals is introduced. Four 32-channel neural recording ICs, complex programmable logic devices (CPLDs), a micro controller unit (MCU) with USB interface, and a PC are used. Each neural recording IC, implemented in $0.18{\mu}m$ CMOS technology, includes 32 channels of analog front-ends (AFEs), a 32-to-1 analog multiplexer, and an analog-to-digital converter (ADC). The mid-band gain of the AFE is adjustable in four steps, and have a tunable bandwidth. The AFE has a mid-band gain of 54.5 dB to 65.7 dB and a bandwidth of 35.3 Hz to 5.8 kHz. The high-pass cutoff frequency of the AFE varies from 18.6 Hz to 154.7 Hz. The input-referred noise (IRN) of the AFE is $10.2{\mu}V_{rms}$. A high-resolution, low-power ADC with a high conversion speed achieves a signal-to-noise and distortion ratio (SNDR) of 50.63 dB and a spurious-free dynamic range (SFDR) of 63.88 dB, at a sampling-rate of 2.5 MS/s. The effectiveness of our neural recording system is validated in in-vivo recording of the primary somatosensory cortex of a rat.

• Laser Solutions
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• v.13 no.4
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• pp.7-13
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• 2010

Today, the most common process for generating Through Silicon Vias (TSVs) for 3D ICs is Deep Reactive Ion Etching (DRIE), which allows for high aspect ratio blind holes with low surface roughness. However, the DRIE process requires a vacuum environment and the use of expensive masks. The advantage of using lasers for TSV drilling is the higher flexibility they allow during manufacturing, because neither vacuum nor lithography or masks arc required and because lasers can be applied even to metal and to dielectric layers other than silicon. However, conventional nanosecond lasers have the disadvantage of causing heat affection around the target area. By contrast, the use of a picosecond laser enables the precise generation of TSVs with less heat affected zone. In this study, we conducted a comparison of thermalization effects around laser-drilled holes when using a picosecond laser set for a high pulse energy range and a low pulse energy range. Notably, the low pulse energy picosecond laser process reduced the experimentally recast layer, surface debris and melts around the hole better than the high pulse energy process.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.8 no.4
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• pp.310-318
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• 2015

In this paper, dual-port eFuse OTP (one-time programmable) memory cells with smaller cell sizes are used, a single VREF (reference voltage) is used in the designed eFuse OTP IP (intellectual property), and a BL (bit-line) sensing circuit using a S/A (sense amplifier) based D F/F is proposed. With this proposed sensing technique, the read current can be reduced to 3.887mA from 6.399mA. In addition, the sensing resistances of a programmed eFuse cell in the program-verify-read and read mode are also reduced to $9k{\Omega}$ and $5k{\Omega}$ due to the analog sensing. The layout size of the designed 32-bit eFuse OTP memory is $187.845{\mu}m{\times}113.180{\mu}m$ ($=0.0213{\mu}m2$), which is confirmed to be a small-area implementation.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.338-338
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• 2013

Monolithic three-dimensional integrated circuits (3D-ICs) 구현 시 bonding 과정에서 발생되는 aluminum (Al) 이나 copper (Cu) 등의 interconnect metal의 확산, 열적 스트레스, 결함의 발생, 도펀트 재분포와 같은 문제들을 피하기 위해서는 저온 공정이 필수적이다. 지금까지는 polymer 기반의 bonding이나 Cu/Cu와 같은 metal 기반의 bonding 등과 같은 저온 bonding 방법이 연구되어 왔다. 그러나 이와 같은 bonding 공정들은 공정 시 void와 같은 문제가 발생하거나 공정을 위한 특수한 장비가 필수적이다. 반면, 두 물질의 합금을 이용해 녹는점을 낮추는 eutectic bonding 공정은 저온에서 공정이 가능할 뿐만 아니라 void의 발생 없이 강한 bonding 강도를 얻을 수 있다. Aluminum-germanium (Al-Ge) 및 aluminum-indium (Al-In) 등의 조합이 eutectic bonding에 이용되어 각각 $424^{\circ}C$ 및 $454^{\circ}C$의 저온 공정을 성취하였으나 여전히 $400^{\circ}C$이상의 eutectic 온도로 인해 3D-ICs의 구현 시에는 적용이 불가능하다. 이러한 metal 조합들에 비해 indium (In)과 tin (Sn)은 각각 $156^{\circ}C$ 및 $232^{\circ}C$로 굉장히 낮은 녹는점을 가지고 있기 때문에 In-Sn 조합은 약 $120^{\circ}C$ 정도의 상당히 낮은eutectic 온도를 갖는다. 따라서 본 연구팀은 In-Sn 조합을 이용하여 $200^{\circ}C$ 이하에서monolithic 3D-IC 구현 시 사용될 eutectic bonding 공정을 개발하였다. 100 nm SiO2가 증착된 Si wafer 위에 50 nm Ti 및 410 nm In을 증착하고, 다른Si wafer 위에 50 nm Ti 및 500 nm Sn을 증착하였다. Ti는 adhesion 향상 및 diffusion barrier 역할을 위해 증착되었다. In과 Sn의 두께는 binary phase diagram을 통해 In-Sn의 eutectic 온도인 $120^{\circ}C$ 지점의 조성 비율인 48 at% Sn과 52 at% In에 해당되는 410 nm (In) 그리고 500 nm (Sn)로 결정되었다. Bonding은 Tbon-100 장비를 이용하여 $140^{\circ}C$, $170^{\circ}C$ 그리고 $200^{\circ}C$에서 2,000 N의 압력으로 진행되었으며 각각의 샘플들은 scanning electron microscope (SEM)을 통해 확인된 후, 접합 강도 테스트를 진행하였다. 추가로 bonding 층의 In 및 Sn 분포를 확인하기 위하여 Si wafer 위에 Ti/In/Sn/Ti를 차례로 증착시킨 뒤 bonding 조건과 같은 온도에서 열처리하고secondary ion mass spectrometry (SIMS) profile 분석을 시행하였다. 결론적으로 본 연구를 통하여 충분히 높은 접합 강도를 갖는 In-Sn eutectic bonding 공정을 $140^{\circ}C$의 낮은 공정온도에서 성공적으로 개발하였다.