• Title/Summary/Keyword: 3-layer thin film

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Wafer-level Vacuum Packaging of a MEMS Resonator using the Three-layer Bonding Technique (3중 접합 공정에 의한 MEMS 공진기의 웨이퍼레벨 진공 패키징)

  • Yang, Chung Mo;Kim, Hee Yeoun;Park, Jong Cheol;Na, Ye Eun;Kim, Tae Hyun;Noh, Kil Son;Sim, Gap Seop;Kim, Ki Hoon
    • Journal of Sensor Science and Technology
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    • v.29 no.5
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    • pp.354-359
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    • 2020
  • The high vacuum hermetic sealing technique ensures excellent performance of MEMS resonators. For the high vacuum hermetic sealing, the customization of anodic bonding equipment was conducted for the glass/Si/glass triple-stack anodic bonding process. Figure 1 presents the schematic of the MEMS resonator with triple-stack high-vacuum anodic bonding. The anodic bonding process for vacuum sealing was performed with the chamber pressure lower than 5 × 10-6 mbar, the piston pressure of 5 kN, and the applied voltage was 1 kV. The process temperature during anodic bonding was 400 ℃. To maintain the vacuum condition of the glass cavity, a getter material, such as a titanium thin film, was deposited. The getter materials was active at the 400 ℃ during the anodic bonding process. To read out the electrical signals from the Si resonator, a vertical feed-through was applied by using through glass via (TGV) which is formed by sandblasting technique of cap glass wafer. The aluminum electrodes was conformally deposited on the via-hole structure of cap glass. The TGV process provides reliable electrical interconnection between Si resonator and aluminum electrodes on the cap glass without leakage or electrical disconnection through the TGV. The fabricated MEMS resonator with proposed vacuum packaging using three-layer anodic bonding process has resonance frequency and quality factor of about 16 kHz and more than 40,000, respectively.

Phase Distribution and Interface Chemistry by Solid State SiC/Ni Reaction

  • Lim, Chang-Sung;Shim, Kwang-Bo;Shin, Dong-Woo;Auh, Keun-Ho
    • The Korean Journal of Ceramics
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    • v.2 no.1
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    • pp.19-24
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    • 1996
  • The phase distribution and interface chemistry by the solid-state reaction between SiC and nickel were studied at temperatures between $550 \;and\; 1250^{\circ}C$ for 0.5-100 h. The reaction with the formation of silicides and carbon was first observed above $650^{\circ}C$. At $750^{\circ}C$, as the reaction proceeded, the initially, formed $Ni_3Si_2$ layer was converted to $Ni_2$Si. The thin nickel film reacted completely with SiC after annealing at $950^{\circ}C$ for 2 h. The thermodynamically stable $Ni_2$Si is the only obsrved silicide in the reaction zone up to $1050^{\circ}C$. The formation of $Ni_2$Si layers with carbon precipitates alternated periodically with the carbon free layers. At temperatures between $950^{\circ}C$ and $1050^{\circ}C$, the typical layer sequences in the reaction zone is determined by quantitative microanalysis to be $SiC/Ni_2$$Si+C/Ni_2$$Si/Ni_2$$Si+C/…Ni_2$Si/Ni(Si)/Ni. The mechanism of the periodic band structure formation with the carbon precipitation behaviour was discussed in terms of reaction kinetics and thermodynamic considerations. The reaction kinetics is proposed to estimate the effective reaction constant from the parabolic growth of the reaction zone.

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Improved Uniformity in Resistive Switching Characteristics of GeSe Thin Film by Ag Nanocrystals

  • Park, Ye-Na;Shin, Tae-Jun;Lee, Hyun-Jin;Lee, Ji-Soo;Jeong, Yong-Ki;Ahn, So-Hyun;Lee, On-You;Kim, Jang-Han;Nam, Ki-Hyun;Chung, Hong-Bay
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.08a
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    • pp.237.2-237.2
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    • 2013
  • ReRAM cell, also known as conductive bridging RAM (CBRAM), is a resistive switching memory based on non-volatile formation and dissolution of conductive filament in a solid electrolyte [1,2]. Especially, Chalcogenide-based ReRAM have become a promising candidate due to the simple structure, high density and low power operation than other types of ReRAM but the uniformity of switching parameter is undesirable. It is because diffusion of ions from anode to cathode in solid electrolyte layer is random [3]. That is to say, the formation of conductive filament is not go through the same paths in each switching cycle which is one of the major obstacles for performance improvement of ReRAM devices. Therefore, to control of nonuniform conductive filament formation is a key point to achieve a high performance ReRAM. In this paper, we demonstrated the enhanced repeatable bipolar resistive switching memory characteristics by spreading the Ag nanocrystals (Ag NCs) on amorphous GeSe layer compared to the conventional Ag/GeSe/Pt structure without Ag NCs. The Ag NCs and Ag top electrode act as a metal supply source of our devices. Excellent resistive switching memory characteristics were obtained and improvement of voltage distribution was achieved from the Al/Ag NCs/GeSe/Pt structure. At the same time, a stable DC endurance (>100 cycles) and an excellent data retention (>104 sec) properties was found from the Al/Ag NCs/GeSe/ Pt structured ReRAMs.

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Effect of annealing temperature of solid electrolyte layer on the electrical characteristics of polymer memristor (고체 전해질 층의 어닐링 온도가 고분자 멤리스터의 전기적 특성에 미치는 영향)

  • Woo-Seok, Kim;Eun-Kyung, Noh;Jin-Hyuk, Kwon;Min-Hoi, Kim
    • Journal of IKEEE
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    • v.26 no.4
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    • pp.705-709
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    • 2022
  • The effect of the annealing temperature of the poly(vinylidene fluoride-trifluoroethylene)(P(VDF-TrFE)) solid electrolyte layer on the electrical properties of the P(VDF-TrFE)-based memristor was analyzed. In morphological analyses, the P(VDF-TrFE) thin film with 200℃ annealing temperature (200P(VDF-TrFE)) was shown to have surface roughness ≈5 times larger and thickness ≈20% smaller than that with 100℃ annealing temperature (100P(VDF-TrFE)). Compared to the 100P(VDF-TrFE) memristor (M100), the set voltage of the 200P(VDF-TrFE) memristor (M200) decreased by ≈50% and the magnitude of its reset voltage increased by ≈30%. Moreover, M200 was found to have better memory retention characteristics than M100. These differences were attributed to relatively strong local electric fields inside M200 compared to M100. This study suggests the importance of the annealing temperature in polymer memristors.

A study of the crystallinity and microstructure of the $Si_{1-X}Ge_X$ alloys deposited on the $SiO_2$at various temperatures ($SiO_2$위에 증착된 $Si_{1-X}Ge_X$합금의 증착온도 변화에 따른 결정성 및 미세구조에 관한 연구)

  • Kim, Hong-Seung;Lee, Jeong-Yong;Lee, Seung-Chang;Gang, Sang-Won
    • Korean Journal of Materials Research
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    • v.4 no.4
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    • pp.416-427
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    • 1994
  • The changes of crystallinity and microstructure and the $Si_{1-x}Ge_x/Sio_2$ interfaces of $Si_{1-x}Ge_x$ alloys deposited on amorphous $SiO_{2}$ were studied as a function of deposition temperature. The crystallinity, microstructure, and compositional uniformity of $Si_{1-x}Ge_x$ alloys deposited on the SiOl at different temperature were investigated by X-ray diffraction and transmission electron microscopy. And $Si_{1-x}Ge_x/Sio_2$ interface were investigated by high-resolution transmission electron microscopy. The $Si_{0.7}Ge_{0.3}/Sio_2$ films were deposited on amorphous $SiO_{2}$ at $300^{\circ}C,400^{\circ}C,500^{\circ}C,600^{\circ}C,$ and $700^{\circ}C$ by Si-MBE. In the film deposited at $300^{\circ}C$, only amorphous phase were observed. In the film deposited at $400^{\circ}C$, both amorphous and polycrystalline films were observed. Both phases were deposited simultaneously, but, at initial film growth, amorphous phase prevailed over polycrystalline phase. As the film thickness increased, the fraction of polycrystalline phase increased. At $500^{\circ}C$, thin amorphous layer was observed at lOnm from $SiO_{2}$ surface. In the films deposited at higher than $600^{\circ}C$, only crystalline phase were observed. Polycrystalline films had columnar structure. Compositional uniformity for deposited films were good regardless of deposition temperature. The interfaces of $Si_{1-x}Ge_x/Sio_2$ were flat, whatever polycrystal or amorphous was deposited on $SiO_{2}$.

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Development of flat panel digital x-ray detectorusing a-Se (비정질 셀레늄을 이용한 평판 Digital X선 검출기 개발)

  • Park, J.K.;Choi, J.Y.;Kang, S.S.;Cha, B.Y.;Jang, G.W.;Choi, J.Y.;Nam, S.H.
    • Korean Journal of Digital Imaging in Medicine
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    • v.6 no.1
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    • pp.24-30
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    • 2003
  • Flat-panel detector(FPD) is the driving force for realizing the next gene ration of x-ray system. In this study, we developed amorphous selenium(a-Se) based flat-panel digital X-ray detector(DXD) for radiography. The prototype detector consists of an amorphous selenium layer and a thin-film transistor(TFT) array. Comparing to other papers1)-4), optimization of amorphous selenium and progress of evaporation were similar. The pixel pitch of fabricated detector was $139{\mu}m$, fill factor was 86%, and the size was 14"${\times}$8.5". Hand and test bar pattern images were acquired. A high modulation transfer function(MTF) factor was obtained: 58% at 3.0 lp/mm.

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Synthesis of Uniformly Doped Ge Nanowires with Carbon Sheath

  • Kim, Tae-Heon;;Choe, Sun-Hyeong;Seo, Yeong-Min;Lee, Jong-Cheol;Hwang, Dong-Hun;Kim, Dae-Won;Choe, Yun-Jeong;Hwang, Seong-U;Hwang, Dong-Mok
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.08a
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    • pp.289-289
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    • 2013
  • While there are plenty of studies on synthesizing semiconducting germanium nanowires (Ge NWs) by vapor-liquid-solid (VLS) process, it is difficult to inject dopants into them with uniform dopants distribution due to vapor-solid (VS) deposition. In particular, as precursors and dopants such as germane ($GeH_4$), phosphine ($PH_3$) or diborane ($B_2H_6$) incorporate through sidewall of nanowire, it is hard to obtain the structural and electrical uniformity of Ge NWs. Moreover, the drastic tapered structure of Ge NWs is observed when it is synthesized at high temperature over $400^{\circ}C$ because of excessive VS deposition. In 2006, Emanuel Tutuc et al. demonstrated Ge NW pn junction using p-type shell as depleted layer. However, it could not be prevented from undesirable VS deposition and it still kept the tapered structures of Ge NWs as a result. Herein, we adopt $C_2H_2$ gas in order to passivate Ge NWs with carbon sheath, which makes the entire Ge NWs uniform at even higher temperature over $450^{\circ}C$. We can also synthesize non-tapered and uniformly doped Ge NWs, restricting incorporation of excess germanium on the surface. The Ge NWs with carbon sheath are grown via VLS process on a $Si/SiO_2$ substrate coated 2 nm Au film. Thin Au film is thermally evaporated on a $Si/SiO_2$ substrate. The NW is grown flowing $GeH_4$, HCl, $C_2H_2$ and PH3 for n-type, $B_2H_6$ for p-type at a total pressure of 15 Torr and temperatures of $480{\sim}500^{\circ}C$. Scanning electron microscopy (SEM) reveals clear surface of the Ge NWs synthesized at $500^{\circ}C$. Raman spectroscopy peaked at about ~300 $cm^{-1}$ indicates it is comprised of single crystalline germanium in the core of Ge NWs and it is proved to be covered by thin amorphous carbon by two peaks of 1330 $cm^{-1}$ (D-band) and 1590 $cm^{-1}$ (G-band). Furthermore, the electrical performances of Ge NWs doped with boron and phosphorus are measured by field effect transistor (FET) and they shows typical curves of p-type and n-type FET. It is expected to have general potentials for development of logic devices and solar cells using p-type and n-type Ge NWs with carbon sheath.

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Preparationand Characterization of Rutile-anatase Hybrid TiO2 Thin Film by Hydrothermal Synthesis

  • Kwon, Soon Jin;Song, Hoon Sub;Im, Hyo Been;Nam, Jung Eun;Kang, Jin Kyu;Hwang, Taek Sung;Yi, Kwang Bok
    • Clean Technology
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    • v.20 no.3
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    • pp.306-313
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    • 2014
  • Nanoporous $TiO_2$ films are commonly used as working electrodes in dye-sensitized solar cells (DSSCs). So far, there have been attempts to synthesize films with various $TiO_2$ nanostructures to increase the power-conversion efficiency. In this work, vertically aligned rutile $TiO_2$ nanorods were grown on fluorinated tin oxide (FTO) glass by hydrothermal synthesis, followed by deposition of an anatase $TiO_2$ film. This new method of anatase $TiO_2$ growth avoided the use of a seed layer that is usually required in hydrothermal synthesis of $TiO_2$ electrodes. The dense anatase $TiO_2$ layer was designed to behave as the electron-generating layer, while the less dense rutile nanorods acted as electron-transfer pathwaysto the FTO glass. In order to facilitate the electron transfer, the rutile phase nanorods were treated with a $TiCl_4$ solution so that the nanorods were coated with the anatase $TiO_2$ film after heat treatment. Compared to the electrode consisting of only rutile $TiO_2$, the power-conversion efficiency of the rutile-anatase hybrid $TiO_2$ electrode was found to be much higher. The total thickness of the rutile-anatase hybrid $TiO_2$ structures were around $4.5-5.0{\mu}m$, and the highest power efficiency of the cell assembled with the structured $TiO_2$ electrode was around 3.94%.

Preparation of Field Effect Transistor with $(Bi,La)Ti_3O_{12}$ Ferroelectric Thin Film Gate ($(Bi,La)Ti_3O_{12}$ 강유전체 박막 게이트를 갖는 전계효과 트랜지스터 소자의 제작)

  • Suh Kang Mo;Park Ji Ho;Gong Su Cheol;Chang Ho Jung;Chang Young Chul;Shim Sun Il;Kim Yong Tae
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2003.11a
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    • pp.221-225
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    • 2003
  • The MFIS-FET(Field Effect Transistor) devices using $BLT/Y_2O_3$ buffer layer on p-Si(100) substrates were fabricated by the Sol-Gel method and conventional memory processes. The crystal structure, morphologies and electrical properties of prepared devices were investigated by using various measuring techniques. From the C-V(capacitance-voltage) data at 5V, the memory window voltage of the $Pt/BLT/Y_2O_3/si$ structure decreased from 1.4V to 0.6V with increasing the annealing temperature from $700^{\circ}C\;to\;750^{\circ}C$. The drain current (Ic) as a function of gate voltages $(V_G)$ for the $MFIS(Pt/BLT/Y_2O_3/Si(100))-FET$ devices at gate voltages $(V_G)$ of 3V, 4V and 5V, the memory window voltages increased from 0.3V to 0.8V as $V_G$ increased from 3V to 5V.

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Performance Characteristics of p-i-n Type Organic Thin-film Photovoltaic Cell with CuPc: $F_4$-TCNQ Hole Transport Layer (CuPc: $F_4$-TCNQ 정공 수송층이 도입된 P-i-n형 유기 박막 태양전지의 성능 특성 연구)

  • Park, So-Hyun;Kang, Hak-Su;Senthilkumar, Natarajan;Park, Dae-Won;Choe, Young-Son
    • Polymer(Korea)
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    • v.33 no.3
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    • pp.191-197
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    • 2009
  • We have investigated the effect of strong p-type organic semiconductor $F_4$-TCNQ-doped CuPc hole transport layer on the performance of p-i-n type bulk heterojunction photovoltaic device with ITO/PEDOT:PSS/CuPc: $F_4$-TCNQ(5 wt%)/CuPc:C60(blending ratio l:l)/C60/BCP/LiF/Al, architecture fabricated via vacuum deposition process, and have evaluated the J-V characteristics, short-circuit current ($J_{sc}$), open-circuit voltage($V_{oc}$), fill factor(FF), and power conversion efficiency(${\eta}_e$) of the device. By doping $F_4$-TCNQ into CuPc hole transport layer, increased absorption intensity in absorption spectra, uniform dispersion of organic molecules in the layer, surface uniformity of the layer, and enhanced injection currents improved the current photovoltaic device with power conversion efficiency(${\eta}_e$) of 0.16%, which is still low value compared to silicone solar cell indicating that many efforts should be made to improve organic photovoltaic devices.