• Journal of Welding and Joining
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• 제12권4호
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• pp.85-101
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• 1994

Effect of Cr, Cu and Ni metal powders addition on the alloyed layer of aluminum alloy (AC2B) has been investigated with the plasma transferred arc (PTA) overlaying process. The overlaying conditions were 125-200A in plasma arc current, 150mm/min in process speed and 5-20g/min in powder feeding rate. Main results obtained are summarized as follows: 1) It was made clear that formation of thick surface alloyed layer on aluminum alloy is possible by PTA overlaying process. 2) The range of optimum alloying conditions were much wider in case of Cu and Ni powder additions than the case of Cr powder addition judging from the surface appearance and the bead macrostructure. 3) Alloyed layer with Cu showed almost the homogeneous microstructure through the whole layer by eutectic reaction. alloyed layers with Cr and Ni showed needle-like and agglomerated microstructures, the structure of which has compound layer in upper zone of bead by peritectic and eutectic-peritectic reactions, respectively. 4) Microconstituents of the alloyed layer were analyzed as A1+CrA $l_{7}$ eutectics, C $r_{2}$al sub 11/, CrA $l_{4}$, C $r_{4}$A $l_{9}$ and C $r_{5}$A $l_{*}$ 8/ for Cr addition, Al+CuA $l_{2}$(.theta.) eutectics and .theta. for Cu addition, and Al+NiA $l_{3}$ eutectics. NiA $l_{3}$, N $i_{2}$A $l_{3}$ and NiAl for Ni addition. 5) Concerning defect of the alloyed layer, many blow holes were seen in Cr and Ni additions although there was lesser in Cu addition. Residual gas contents in blow hole for Cu and Ni alloyed layer were confirmed as mainly $H_{2}$ and a littie of $N_{2}$ Cracking was observed in compound zone of the alloyed layer in case of Cr and Ni addition but not in Cu alloyed layer.r.r.

• 한국주조공학회지
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• 제2권3호
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• pp.2-15
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• 1982

In this study, the influenced of graphite shape on the boriding of cast iron and boride structure was investigated. Gray cast iron, ferritic and pearlitic ductile cast iron were borided at 750,850,900 and $950^{\circ}C$ for 1,3 and 5 hours by powder pack method with the mixture of $B_4C_9\;Na_2B_4O_7$, $KBF_4$ and Shc. The boride layer was consisted of FeB(little), $Fe_2B$ (main) and graphite. Some possibility of the existence of unknown Fe-B-C compound in the boride layer was suggested. And precipitates in the diffusion zone was $Fe_3(B,C)$. The concentration of Si and precipitation of $Fe_3(B,C)$ in the ${\alpha}$ layer raised the hardness of this Zone. The depth and hardness of boride layer increased with the increase of treating temperature and tim. But high temperature (over $950^{\circ}C)$ caused pore at graphite position and long treating time (5hrs) sometimes caused formation of graphite layer beneath the boride layer. So, for the practical application of borided cast iron, treating in short time and at low temperature was recommended. And for ductile cast iron, ferritizing or pearlitizing heat treatment was seemmed to be possible at the same time with boriding. The graphite in the boride layer was deeply concerned with the qualitx and characteristics of the boride layer. And it greatly influenced on the shape of the boride phase, structure of the boride layer. Generally speaking, the existance of graphite restrained the growth of the boride phase. But the boundary between the gsaphite and the matrix acted as the shortcut of boron diffusion. So, for gray cast iron, the graphite layed length-wise led the formation of boride layer.

• 한국전기전자재료학회논문지
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• 제19권9호
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• pp.878-882
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• 2006

We have fabricated single organic layer devices of the organolanthanide complex, terbium tris-(1-phenyl-3-methyl-4-(tertiarybutyry)pyrazol-5-one)triphenylphosphine oxide [$(tb-PMP)_{3}Tb-(Ph_{3}PO)$] for the investigation of its light emission and electrical conduction properties. The thickness of ($(tb-PMP)_{3}Tb-(Ph_{3}PO)$) layer was varied to 60, 75, 95 nm. Mg and Ca layers were used for the cathode contact. The electrical conduction in the $(tb-PMP)_{3}Tb-(Ph_{3}PO)$ single layer devices was dominated by the injection of electrons into the organic layer from the cathode. A higher current density at much lower voltages can be attained with Ca cathode because of the enhanced electron injection. The device shows very sharp emission at 548 nm. The FWHM of the strongest emission peak was 12 nm.

• Journal of the Korean Wood Science and Technology
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• 제27권3호
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• pp.82-90
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• 1999

송광사 삼세불화는 조성년도가 확실하지 않지만 남아있는 서기(書記)와 재질 분석을 통해 19세기초에 제작된 것으로 추정 할 수 있었다. 그리고 공시불화의 보존처리를 위해 안료층과 바탕층, 지지층을 구성하고 있는 재질을 분석하고 이에 적합한 지지층인 배첩지를 초지하여 그 적합성을 시험한 바 다음과 같은 결론을 얻었다. 1. 삼세불화의 단면구조는 안료층과 명주로 된 바탕층 그리고 한지(韓紙)로 이루어진 지지층으로 구성되어 있어 19세기 당시의 불화는 기본적으로 안료층, 바탕층, 지지층으로 구성되어 있음을 알 수 있었다. 또한 안료층과 바탕층의 접착은 아교를 사용하였고 지지층의 sheet 배첩은 호료(糊料)를 사용했음을 알 수 있었다. 2. 삼세불화의 지지층은 5겹으로 구성되어 있고 두 종류의 종이가 사용되었는데 바탕층과 접해 있는 1~2층은 순수한 닥섬유로 제조한 한지(韓紙)를 사용하였고 나머지 3개 층은 폐마섬유(廢麻纖維)에 닥섬유가 혼합된 종이를 사용하였다. 더 많은 자료가 확보되어야만 단언할 수 있지만 재질을 통해 당시의 상황을 파악해 보면 19세기 당시의 사회는 경제적으로 어려움을 겪고 있었고 더욱이 사찰 제지업은 피폐해져 운영이 어려워 후면에 사용한 배첩지는 질이 떨어지는 폐마를 이용 했을 것으로 추측되었다. 3. 본 재료의 바탕층과 지지층간의 인장력을 고려하여 새롭게 제조해 보수용으로 사용한 바 본 공시재료의 보수용 배첩지로서 적합했음을 알 수 있었다.

• 한국진공학회지
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• 제16권3호
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• pp.215-220
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• 2007

[ $Pt/SBT/Seed/Pt/Ti/SiO_2/Si$ ]의 구조로 $SBT(SrBi_2Ta_2O_9)$ 박막을 Self-seed layer를 사용하여 R.F. Magnetron sputter를 이용하여 증착을 하였다. Self-seed layer는 기판온도 RT(room temperature)와 $600^{\circ}C$에서 두께 30 nm으로 증착하였다. Self-seed layer의 결정화 온도를 알아보기 위해 열처리온도를 변화시켰고 이를 XRD를 통하여 결정화 유무를 확인하였다. Self-seed layer 위에 증착한 SBT를 XRD와 전기적 측정을 통해 특성을 관찰하였다.

• Journal of Information Display
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• 제4권1호
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• pp.29-33
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• 2003

We have investigated the effects of hole-injection buffer layer in organic light-emitting diodes using copper phthalocyanine (CuPc), poly(vinylcarbazole)(PVK), and Poly(3,4-ethylene dioxythiophene):poly(styrenesulfonate) (PEDOT: PSS) in a device structure of $ITO/bufferr/TPD/Alq_3/Al$. Polymer PVK and PEDOT:PSS buffer layer were produced using the spin casting method where as the CuPc layer was produced using thermal evaporation. Current-voltage characteristics, luminance-voltage characteristics and efficiency of device were measured at room temperature at various a thickness of the buffer layer. We observed an improvement in the external quantum efficiency by a factor of two, four, and two and half when the CuPc, PVK, and PEDOT:PSS buffer layer were used, respectively. The enhancement of the efficiency is assumed to be attributed to the improved balance of holes and elelctrons resulting from the use of hole-injection buffer layer. The CuPc and PEDOT:PSS layer function as a hole-injection supporter and the PVK layer as a hole-blocking one.

• 한국전기전자재료학회논문지
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• 제22권10호
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• pp.850-853
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• 2009

We have optimized the device structure by using the dielectric layer such as anti-reflection thin film to improve the emitting efficiency of white organic light emitting device (WOLED). Basically, dielectric layer with anti-reflection characteristics can enhance the emitting efficiency of WOLED by compensating the refractive index of organic layer, ITO, and Glass. Here, WOLED was designed and optimized by Macleod simulator. The refractive index of 1.74 was calculated for Dielectric layer and was selected as $TiO_2$. The optimal thicknesses of $TiO_2$ and ITO were 119.3 and 166.6 nm, respectively, at the wavelength of 600 nm. The transmittance of ITO was measured with the thickness variation of dielectric layer and ITO in Organic layer/ITO/Dielectric layer structure. The transmittance of ITO was 95.17% and thicknesses of $TiO_2$ and ITO were 119.3 and 166.6 nm, respectively. This result, calculated and measured values were coincided.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.601-608
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• 2014

In this paper, we have characterized the electrical properties related to gate leakage current in AlGaN/GaN MISHFETs with varying the thickness (0 to 10 nm) of $Al_2O_3$ gate insulator which also serves as a surface protection layer during high-temperature RTP. The sheet resistance of the unprotected TLM pattern after RTP was rapidly increased to $1323{\Omega}/{\square}$ from the value of $400{\Omega}/{\square}$ of the as-grown sample due to thermal damage during high temperature RTP. On the other hand, the sheet resistances of the TLM pattern protected with thin $Al_2O_3$ layer (when its thickness is larger than 5 nm) were slightly decreased after high-temperature RTP since the deposited $Al_2O_3$ layer effectively neutralizes the acceptor-like states on the surface of AlGaN layer which in turn increases the 2DEG density. AlGaN/GaN MISHFET with 8 nm-thick $Al_2O_3$ gate insulator exhibited extremely low gate leakage current of $10^{-9}A/mm$, which led to superior device performances such as a very low subthreshold swing (SS) of 80 mV/dec and high $I_{on}/I_{off}$ ratio of ${\sim}10^{10}$. The PF emission and FN tunneling models were used to characterize the gate leakage currents of the devices. The device with 5 nm-thick $Al_2O_3$ layer exhibited both PF emission and FN tunneling at relatively lower gate voltages compared to that with 8 nm-thick $Al_2O_3$ layer due to thinner $Al_2O_3$ layer, as expected. The device with 10 nm-thick $Al_2O_3$ layer, however, showed very high gate leakage current of $5.5{\times}10^{-4}A/mm$ due to poly-crystallization of the $Al_2O_3$ layer during the high-temperature RTP, which led to very poor performances.

• 대한전자공학회논문지
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• 제23권5호
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• pp.699-705
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• 1986

Sb2S3 thin films were fabricated by vacuum evaporation of compound Sb2S3 at a pressure of 10**-5 torr. and in argon ambient. Then, their electrical and photoconductive properties were investigated. The Sb2S3 glass-layer showed maximum photosensitivity at the deposition rate of 250\ulcornersec, and Sb2S3 porous layer had mininum dielectric constant of 1.5 at the deposition rate of 0.3 um/sec and argon partial pressure of 0.2torr. Sb2S3 multi-layers were prepared at the different thickness ratio (B/A) to find the proper structural property suited for camera pick-up tube. Here, A is the sum of the thickness of Sb2S3 porous layer and Sb2S3 fine grain layer, and B is the thickness of Sb2S3 fine grain layer. As a result, photosensitivity had a peak value at the thickness ratio (B/A) of 60%.

• 한국정보통신학회논문지
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• 제14권3호
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• pp.621-627
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• 2010

본 논문에서는 SVC 복호화기에서 각 계층간 Inter layer 업-샘플링을 효과적으로 구현하기 위한 하드웨어 구조를 제안한다. 제안하는 구조에서 수직, 수평 방향 업-샘플링을 위한 register bank와 보간 모듈이 설계된다. 제안 구조를 사용하여 SRAM 메모리가 감소되고 JSVM과 비교해서 약 41%의 메모리 밴드위스가 감소되었다.