• Journal of IKEEE
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• v.18 no.1
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• pp.37-44
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• 2014

In this paper we present an LDO based on an error amplifier. The designed error amplifier has a gain of 89.93dB at low frequencies. This amplifier's Bandwidth is 50.8MHz and its phase margin is $59.2^{\circ}C$. Also we proposed a BGR. This BGR has a low output variation with temperature and its PSRR at 1 KHz is -71.5dB. For a temperature variation from $-40^{\circ}C$ to $125^{\circ}C$ we have just 9.4mV variation in 3.3V LDO output. Also it is stable for a wide range of output load currents [0-200mA] and a $1{\mu}F$ output capacitor and its line regulation and especially load regulation is very small comparing other papers. The PSRR of proposed LDO is -61.16dB at 1 KHz. Also we designed it for several output voltages by using a ladder of resistors, transmission gates and a decoder. Low power consumption is the other superiority of this LDO which is just 1.55mW in full load. The circuit was designed in $0.35{\mu}m$ CMOS process.

• Journal of the Korea Institute of Military Science and Technology
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• v.11 no.3
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• pp.146-153
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• 2008

High-power communication jammer has to include the switched filter bank to eliminate the harmonic signals generated by amplifier. Generally, the switched filter bank consists of in-out switches and several filters. This paper describes the design of high-power switched filter bank, particularly the high-power filter bank operating over 20$\sim$110MHz frequency range. The filters designed have insertion loss less than 0.3dB, VSWR less than 1.25:1, and harmonic suppression more than 35dB. Also, the switched filter bank can endure upto 2kW high-power signal with very low harmonic level within $30{\mu}s$ switching speed.

• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1577-1579
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• 1994

200-MW pulse modulators(total 11units) for the PLS linac employ the SCR phase control circuit. It controls 3-phase AC line voltage for the high-voltage DC power supply (DCPS, maximum of 25kVDC, 4.2A) which charges the pulse forming network(PFN). The PFN delivers 400kV, 500A, ESW $7.5{\mu}s$ pulse power to the 80-MW klystron amplifier tube. The SCR regulates 3-phase AC power and feeds to the high voltage transformer. Two different types of the transformer configurations namely ${\Delta}-{\Delta}$ and ${\Delta}-Y$, are alternatively installed to 11 modulator units for the suppression of harmonic noises. RC filters and reactors are also installed. Currently, approximately 110-kW of average AC power per unit is consumed at the normal operation level of the modulator with 30pps. This paper presents the operational characteristics of the high power pulse modulator, especially the experimental results of the AC line harmonic components generated by the operation of the high power pulse modulator to suppress the switching noises from the SCR and rectifying diode arrays.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.49-58
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• 2014

A low-swing differential near-ground signaling (NGS) transceiver for low-power high-speed mobile I/O interface is presented. The proposed transmitter adopts an on-chip regulated programmable-swing voltage-mode driver and a pre-driver with asymmetric rising/falling time. The proposed receiver utilizes a new multiple gain-path differential amplifier with feed-forward capacitors that boost high-frequency gain. Also, the receiver incorporates a new adaptive bias generator to compensate the input common-mode variation due to the variable output swing of the transmitter and to minimize the current mismatch of the receiver's input stage amplifier. The use of the new simple and effective impedance matching techniques applied in the transmitter and receiver results in good signal integrity and high power efficiency. The proposed transceiver designed in a 65-nm CMOS technology achieves a data rate of 13 Gbps/channel and 0.3 pJ/bit (= 0.3 mW/Gbps) high power efficiency over a 10 cm FR4 printed circuit board.

• Journal of the Korea Institute of Military Science and Technology
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• v.19 no.5
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• pp.574-581
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• 2016

Trend on high-power GaN(Gallium Nitride) SSPA(Solid-State Power Amplifier) and its availability in miniature radar systems are presented. There are numerous studies on high-power GaN devices since they have some characteristics of high-breakdown voltage, high power density, and high-temperature stability. Recent scaled GaN technology makes it possible to apply it in SSPAs for W- and G-band applications, with increasing its maximum frequency. In addition, it leads to downsizing and power-efficiency improvement of SSPAs, which means that GaN SSPAs can be available in miniature radar systems. This study also shows radar performance and comparison in the case of using such SSPAs at three frequency bands of Ku, Ka, and W. Finally, we demonstrate prospects of scaled GaN SSPAs in future miniature radar systems.

• Proceedings of the KAIS Fall Conference
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• 2010.11a
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• pp.168-171
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• 2010

본 논문에서는 GaN HEMT 소자를 이용한 고출력 고효율 특성을 가지는 광대역 SSPA의 개발을 다루고 있다. 개발한 SSPA는 8W 급과 15W 급의 GaN HEMT 소자를 사용하여 Pre-Drive 증폭단을 구성하였으며, Drive 증폭단은 50W/150W급 GaN HEMT 소자를 직/병렬구조로 사용하였다. Main 증폭단은 4-way 분배기와 결합기를 이용한 Balanced Structure를 적용하여 높은 출력을 구현하였으며, 안정적인 동작을 위하여 음(-)전원 제어 회로와 출력신호 검출 회로를 포함하고 있다. 제작된 SSPA의 사용가능 대역은 2.9GHz~3.3GHz로 단일전원을 사용하고 있으며 100us 펄스 폭, 10% Duty Cycle 조건에서 60dB의 전압이득, 1kW 출력과 약 28% 효율 특성을 가지는 것으로 측정되었다. 본 논문에서 개발한 SSPA는 S-대역을 사용하는 레이더시스템의 송신단에 적용될 수 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.334-341
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• 2015

This research outlines the design of a HR-TDC (High Resolution Time-to-Digital Converter) for high data rate communication systems using a $0.18{\mu}m$ CMOS process. The coarse-fine architecture has been adopted to improve the resolution of the TDC. A two-stage vernier time amplifier (2S-VTA) was used to amplify the time residue, and the gain of the 2S-VTA was larger than 64. The error during time amplification was compensated using two FTDCs (Fine-TDC) with their outputs. The resolution of the HR-TDC was 0.15 ps with a 12-bit output and the power consumption was 4.32 mW with a 1.8-V supply voltage.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.545-548
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• 2004

The paper describes the design of high-speed, high-resolution Sample-and-Hold circuit which shows the conversion rate 80MHz and the power supply of 3.3v with 0.35um CMOS 2-poly 4-metal process for high-speed, high resolution Analog-to-Digital Converter. For improving Dynamic performance of Sample-and-Hold, Two Double bootstrap switch and high performance operational amplifier with gain booster, which are used. and For physical stability of Sample and Hold circuit, reduces excess voltage of gate in bootstrap switch. Simulation results using HSPICE shows the SFDR of 71dB, 75dB in conversion rate of 80MHz result for two inputs(0.5Vpp, 10MHz and 1Vpp, 10MHz) and the power dissipation of 48mW at single 3.3V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.26-34
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• 2007

This Paper describes a chip design technique for body composition analyzer based on the BIA (Bioelectrical Impedance Analysis) method. All the functions of signal forcing circuits to the body, signal detecting circuits from the body, Micom, SRAM and EEPROMS are integrated in one chip. Especially, multi-frequency detecting method can be applied with selective band pass filter (BPF), which is designed in weak inversion region for low power consumption. In addition new full wave rectifier (FWR) is also proposed with differential difference amplifier (DDA) for high performance (small die area low power consumption, rail-to-rail output swing). The prototype chip is implemented with 0.35um CMOS technology and shows the power dissipation of 6 mW at the supply voltage of 3.3V. The die area of prototype chip is $5mm\times5mm$.

• Journal of KSNVE
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• v.9 no.5
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• pp.1036-1041
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• 1999

This paper aims for the development of the high power sonar system for measuring the velocity of a moving object. The high power sonar system transmits two gated 190 kHz sinusoidal signals with 1.6 [ms] time interval to the moving object. Then the sonar system detects and calculates the changed time delay of the reflected ultrasonic signals in order to derive the velocity of the moving object. The transmission part uses a high power amplifier so that 250 W gated sinusoidal signals can be transmitted to the transmitter. 1M RAM is utilized for transmitting and storing of the ultrasonic signals. The time delay is calculted by the cross-correlation technique between the transmitted signals and the received signals. The measured value from the high power sonar system is compared with directly measured values by photo diodes. The result confirms the adjacency to 0.3% error.