• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1891-1898
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• 2013

To efficiently execute 3D graphic APIs, such as OpenGL and Direct3D, special purpose arithmetic unit(SFU) which supports floating-point sine, cosine, reciprocal, inverse square root, base-two exponential, and logarithmic operations is designed. The SFU uses second order minimax approximation method and lookup table method to satisfy both error less than 2 ulp(unit in the last place) and high speed operation. The designed circuit has about 2.3-ns delay time under 65nm CMOS standard cell library and consists of about 23,300 gates. Due to its maximum performance of 400 MFLOPS and high accuracy, it can be efficiently applicable to mobile 3D graphics application.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.101-109
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• 2009

Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.59-70
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• 2007

In this paper, we proposed an effective T&L(Transform & Lighting) Processor architecture for a real time 3D graphics acceleration SoC(System on a Chip) in a mobile system. We designed Floating point arithmetic IPs for a T&L processor. And we verified IPs using a SoC Platform. Designed T&L Processor consists of 24 bit floating point data format and 16 bit fixed point data format, and supports the pipeline keeping the balance between Transform process and Lighting process using a parallel computation of 3D graphics. The delay of pipeline processing only Transform operation is almost same as the delay processing both Transform operation and Lighting operation. Designed T&L Processor is implemented and verified using a SoC Platform. The T&L Processor operates at 80MHz frequency in Xilinx-Virtex4 FPGA. The processing speed is measured at the rate of 20M Vertexes/sec.

• Journal of The Korean Association For Science Education
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• v.34 no.6
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• pp.601-611
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• 2014

The purpose of this study is to analyze the Korean science magazine, Science Donga providing scientific facts, phenomenons, and issues with infographic for the readers by time series analysis and to search for the application of infographic on the science education. The criteria for the infographic analysis of Science Donga consisted of three categories such as storytelling type, visual perception, and framework level because infographic presents complex information quickly and clearly by integrating various images, words, and graphics. We found that the articles emphasized by including image about science issue have been published from 1986 to 2014. Particularly, after 2008, the articles including infographic sharply rose. So we set up 2008 as $T_c$(Critical time point). The articles including infographic after 2008 have been more variously distributed and frequently used in storytelling types category such as location, time, number, connection, function, and process based infographic, in visual perception of Gestalt Theory such as proximity, similarity, continuation, and closure than before 2008. Lastly, in framework level category, location, time, number, and process based infographic mainly had total range level but function and connection based infographic changed in the framework level. The three features about storytelling type, visual perception, framework level are important changes to influence $T_c$ in the infographic analysis about Science Donga. Through the results of this study, we analyzed the feature of change on infographic from 1986 to 2014. Thus, we hope that the results suggest a basic criteria for making materials including infographic in science education.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.11
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• pp.2107-2115
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• 2007

In this paper, the scan conversion processor which converts the triangle represented by three vertices into pixel-level screen coordinates, depth coordinate, and color data is designed. The processor adopts scan-line algorithm which decomposes triangle into horizontal spans and then transforms the span into pixel data. By supporting top-left filling convention, it ensures that triangles that share an edge do not produce any dropouts or overlaps between adjacent polygons. It consists of about 21,400 gates and its maximum operating frequency is about 80 Mhz under 0.35um CMOS technology. Because its maximum pixel rate is about 80 Mpixels/sec, it can be applicable to mobile graphics application.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.140-142
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• 2011

In this paper, special purpose arithmetic unit for mobile graphics accelerator is designed. The designed processor supports six operations, such as $1/{\chi}$, $\frac{1}{{\sqrt{x}}$, $log_2x$, $2^x$, $sin(x)$, $cos(x)$. The processor adopts 2nd-order polynomial minimax approximation scheme based on IEEE floating point data format to satisfy accuracy conditions and has 5-stage pipeline structure to meet high operational rates. The SFAU processor consists of 23,000 gates and its estimated operating frequency is about 400 Mhz at operating condition of 65nm CMOS technology. Because the processor can execute all operations with 5-stage pipeline scheme, it has about 400 MOPS(million operations per second) execution rate. Thus, it can be applicable to the 3D mobile graphics processors.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.912-920
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• 2002

As computer systems and communication technologies develop rapidly, CSCW(Computer Supported Collaborative Work) system appears nowadays, through which it is available to work on virtual space without any restriction of time and place. Most of CWCS systems depend on a special network and groupware. The systems of graphics and CAD are not so many because they are specified by hardware and application software. We propose a Web-based collaborative CAD system which is independent from any platforms, and develop a 3D solid modeler in the system. This system can be worked in the environment of Client/Server architecture. Clients connect to the design server through Java applet on WWW. The server is implemented by Java application.

• Transactions of the Korean Society of Mechanical Engineers
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• v.19 no.2
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• pp.568-579
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• 1995

An off-line programming (OLP) system was proposed and developed in order to save cost and time in adjusting a robot to new workcells or applying new algorithms to actual trajectory planning. The developed OLP system was especially designed to be operated in a PC level host computer. A SCARA robot with four axes was selected as an objective robot. The OLP system developed in this study consisted of such modules as data base, three-dimensional graphics, kinematics, trajectory planning, dynamics, control, and commands. Each module was constructed to form an independent unit so that it can be easily modified or improved. The OLP system was programmed for a graphic user interface in Borland $C^{++}$ language. Some of system operating commands and an interpreter were devised and used for more convenient programming of robot simulations.s.