• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.24 no.9
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• pp.682-686
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• 2014

Nowadays, the needs to revise the classification criteria for noise emission facilities have been suggested by the related industries. Because there existed many reasonable factors in the criteria regarding the noise emission facilities. And the noise emission facility classification criterion of the print machine changed from 50 HP to 100 HP in 2013. But the increasement of the noise emission facility classification criterion of the print machine can cause adverse effects like the bigger noise. So, in this paper, we measured the print machine's sound power level according to the changes of the print machine's power to assess the adverse effects. The measurement method applied with KS I ISO 9614-2(1996). The corelation between the sound power level and the power of print machines was analyzed by regression analysis. In this paper, we found that the sound power level of the print machines can increase about 1.3 dB in the condition of that the power of print machine increases from 50 HP to 100 HP. And we found that the sound power level of the print machines can increase about 1.0 dB for a increasement of 1,000 SPH(sheet per hour) of printing speed. The noise emission characteristics of print machine stuied in this paper will be useful to design the noise reduction plan in the future.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.183-192
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• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.

• Journal of the Korea Furniture Society
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• v.20 no.5
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• pp.467-479
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• 2009

The high-tech computer technology developments have greatly affected the area of design education. Starting from the mid 80s, innovations in visual presentation methods have heightened with 2D computer graphic programs, CAD & 3D modeling, and Rapid Prototype that allows dimensional generation. The specialty and quality in design studio education have advanced due to the development in presentation methods such as Power Point and Keynote. But there are many problems with the current method of presenting the visual outcome in a data format using beam projectors, which is a vertical presenting method compared to the old studio study method of conducting discussions and reviews based on the substantial outcome. The essence of studio study that allows for comparisons and analysis by horizontally opening up the various work outcomes is being offset. Also the requirement for manual idea sketching work that plays an important role in the initial design phase continuing to decrease due to the digital working process dependence and cumbersome procedures in the presentation. In order to resolve this problem, the CALM system (Class Applied LCD Modular System) has been developed that replaces the method of attaching the sketches or renderings on the wall with a digital multi-display system. In a nutshell, individuals will upload the outcomes online and display them on the CALM system studio that is composed of 32 LCD (Columns: 4 $\times$ Rows: 8) monitors that are 19 inches in size so that various personnel can openly study the design outcomes. Also the central 42 inch PDP monitor that offers touch pad capability allows each design outcome to be described and examined by expanding. The concept phase of this development process has elevated to the production of an operating prototype that is being reviewed of its practicality. It is considered that the development of this system will decrease the extreme tendency of depending on digital operation but achieve revitalization of a more realistic and opened studio study environment compared to the individual consulting method of the old study approach.

• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.404-416
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• 2015

Small-area, low-power coarse and fine frequency detectors (FDs) are proposed for an adaptive bandwidth referenceless CDR with a wide range of input data rate. The coarse FD implemented with two flip-flops eliminates harmonic locking as long as the initial frequency of the CDR is lower than the target frequency. The fine FD samples the incoming input data by using half-rate four phase clocks, while the conventional rotational FD samples the full-rate clock signal by the incoming input data. The fine FD uses only a half number of flip-flops compared to the rotational FD by sharing the sampling and retiming circuitry with PLL. The proposed CDR chip in a 65-nm CMOS process satisfies the jitter tolerance specifications of both USB 3.0 and USB 3.1. The proposed CDR works in the range of input data rate; 2 Gb/s ~ 8 Gb/s at 1.2 V, 4 Gb/s ~ 11 Gb/s at 1.5 V. It consumes 26 mW at 5 Gb/s and 1.2 V, and 41 mW at 10 Gb/s and 1.5 V. The measured phase noise was -97.76 dBc/Hz at the 1 MHz frequency offset from the center frequency of 2.5 GHz. The measured rms jitter was 5.0 ps at 5 Gb/s and 4.5 ps at 10 Gb/s.

• Nuclear Engineering and Technology
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• v.51 no.5
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• pp.1417-1427
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• 2019

In this study, we evaluated the performance of a commercial pixelated cadmium zinc telluride (CZT) detector for spectroscopy and identified its feasibility as a Compton camera for radiation monitoring in a nuclear power plant. The detection system consisted of a $20mm{\times}20mm{\times}5mm$ CZT crystal with $8{\times}8$ pixelated anodes and a common cathode, in addition to an application specific integrated circuit. The performance of the various radioisotopes $^{57}Co$, $^{133}Ba$, $^{22}Na$, and $^{137}Cs$ was evaluated. In general, the amplitude of the induced signal in a CZT crystal depends on the interaction position and material non-uniformity. To minimize this dependency, a drift time correction was applied. The depth of each interaction was calculated by the drift time and the positional dependency of the signal amplitude was corrected based on the depth information. After the correction, the Compton regions of each spectrum were reduced, and energy resolutions of 122 keV, 356 keV, 511 keV, and 662 keV peaks were improved from 13.59%, 9.56%, 6.08%, and 5%-4.61%, 2.94%, 2.08%, and 2.2%, respectively. For the Compton imaging, simulations and experiments using one $^{137}Cs$ source with various angular positions and two $^{137}Cs$ sources were performed. Individual and multiple sources of $^{133}Ba$, $^{22}Na$, and $^{137}Cs$ were also measured. The images were successfully reconstructed by weighted list-mode maximum likelihood expectation maximization method. The angular resolutions and intrinsic efficiency of the $^{137}Cs$ experiments were approximately $7^{\circ}-9^{\circ}$ and $5{\times}10^{-4}-7{\times}10^{-4}$, respectively. The distortions of the source distribution were proportional to the offset angle.

• Kidney Research and Clinical Practice
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• v.36 no.2
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• pp.145-157
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• 2017

Background: Vitamin D is considered to exert a protective effect on various renal diseases but its underlying molecular mechanism remains poorly understood. This study aimed to determine whether paricalcitol attenuates inflammation and apoptosis during lipopolysaccharide (LPS)-induced renal proximal tubular cell injury through the prostaglandin $E_2$ ($PGE_2$) receptor EP4. Methods: Human renal tubular epithelial (HK-2) cells were pretreated with paricalcitol (2 ng/mL) for 1 hour and exposed to LPS ($1{\mu}g/mL$). The effects of paricalcitol pretreatment in relation to an EP4 blockade using AH-23848 or EP4 small interfering RNA (siRNA) were investigated. Results: The expression of cyclooxygenase-2, $PGE_2$, and EP4 were significantly increased in LPS-exposed HK-2 cells treated with paricalcitol compared with cells exposed to LPS only. Paricalcitol prevented cell death induced by LPS exposure, and the cotreatment of AH-23848 or EP4 siRNA offset these cell-protective effects. The phosphorylation and nuclear translocation of p65 nuclear factor-kappaB ($NF-{\kappa}B$) were decreased and the phosphorylation of Akt was increased in LPS-exposed cells with paricalcitol treatment. AH-23848 or EP4 siRNA inhibited the suppressive effects of paricalcitol on p65 $NF-{\kappa}B$ nuclear translocation and the activation of Akt. The production of proinflammatory cytokines and the number of terminal deoxynucleotidyl transferase-mediated dUTP nick end labeling-positive cells were attenuated by paricalcitol in LPS exposed HK-2 cells. The cotreatment with an EP4 antagonist abolished these anti-inflammatory and antiapoptotic effects. Conclusion: EP4 plays a pivotal role in anti-inflammatory and antiapoptotic effects through Akt and $NF-{\kappa}B$ signaling after paricalcitol pretreatment in LPS-induced renal proximal tubule cell injury.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.2
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• pp.73-78
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• 2020

In this study, a novel reactive power control scheme is proposed to supply stable reactive power to the distribution line by compensating a ripple voltage of DC link. In a single-phase system, a magnitude of second harmonic is inevitably generated in the DC link voltage, and this phenomenon is further increased when the capacity of DC link capacitor decreases. Reactive power control was performed by controlling the d-axis current in the virtual synchronous reference frame, and the voltage control for maintaining the DC link voltage was implemented through the q-axis current control. The proposed method for compensating the ripple voltage was classified into three parts, which consist of the extraction unit of DC link voltage, high pass filter (HPF), and time delay unit. HPF removes an offset component of DC link voltage extracted from integral, and a time delay unit compensates the phase leading effect due to the HPF. The compensated DC voltage is used as feedback component of voltage control loop to supply stable reactive power. The performance of the proposed algorithm was verified through simulation and experiments. At DC link capacitance of 375 uF, the magnitude of ripple voltage decreased to 8 Vpp from 74 Vpp in the voltage control loop, and the total harmonic distortion of the current was improved.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.117-124
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• 2009

This paper describes a 3 to 5 GHz frequency synthesizer for MB-OFDM (Multi-Band OFDM) UWB (Ultra- Wideband) application using 0.13 ${\mu}m$ CMOS process. The frequency synthesizer operates in the band group 1 whose center frequencies are 3432 MHz 3960 MHz, and 4488 MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and LO Mixer architecture are also presented in this paper. A new mixed coarse tuning scheme that utilizes the MIM capacitance, the varactor arrays, and the DAC is proposed to expand the VCO tuning range. The frequency synthesizer can also provide the clock for the ADC in baseband modem. So, the PLL for the ADC in the baseband modem can be removed with this frequency synthesizer. The single PLL and two SSB-mixers consume 60 mW from a 1.2 sV supply. The VCO tuning range is 1.2 GHz. The simulated phase noise of the VCO is -112 dBc/Hz at 1 MHz offset. The die area is 2 ${\times}$ 2mm$^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.34-41
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• 2011

This paper presents a wide tuning range, fine-resolution DCO (Digitally Controlled Oscillator) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. To cover the wide tuning range, an automatic three-step coarse tuning scheme is proposed. The DCO total frequency tuning range is 1.4 GHz (2.1 GHz to 3.5 GHz), it is 58 % at 2.4 GHz. An effective frequency resolution is 0.14 kHz/LSB. The proposed DCO is implemented in 0.13 ${\mu}m$ CMOS process. The total power consumption is 6.6 mW from a 1.2 V supply voltage. The phase noise of the DCO output at 2.4 GHz is -120.67 dBc/Hz at 1 MHz offset.