• Title/Summary/Keyword: 2D Array

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2D Sparse Array Transducer Optimization for 3D Ultrasound Imaging

  • Choi, Jae Hoon;Park, Kwan Kyu
    • Journal of the Korean Society for Nondestructive Testing
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    • v.34 no.6
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    • pp.441-446
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    • 2014
  • A 3D ultrasound image is desired in many medical examinations. However, the implementation of a 2D array, which is needed for a 3D image, is challenging with respect to fabrication, interconnection and cabling. A 2D sparse array, which needs fewer elements than a dense array, is a realistic way to achieve 3D images. Because the number of ways the elements can be placed in an array is extremely large, a method for optimizing the array configuration is needed. Previous research placed the target point far from the transducer array, making it impossible to optimize the array in the operating range. In our study, we focused on optimizing a 2D sparse array transducer for 3D imaging by using a simulated annealing method. We compared the far-field optimization method with the near-field optimization method by analyzing a point-spread function (PSF). The resolution of the optimized sparse array is comparable to that of the dense array.

Design of Circularly Polarized Array Antenna for 5.8GHz Microwave Wireless Power Transmission (5.8GHz 마이크로파 무선전력전송을 위한 원형 편파 배열 안테나 설계)

  • Lee, Seong Hun;Son, Myung Sik
    • Journal of the Semiconductor & Display Technology
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    • v.17 no.2
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    • pp.20-25
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    • 2018
  • In this paper, we have designed circularly polarized array antenna for 5.8GHz microwave wireless power transmission. To obtain high antenna gain, we studied a single patch antenna, a $2{\times}1$ array antenna, a $2{\times}2$ array antenna, a $2{\times}4$ array antenna, and a $4{\times}4$ array antenna. Commonly, characteristics of each antenna have a frequency of 5.8 GHz and Right Hand Circular Polarization(RHCP) of circular polarization. Also, the results were obtained with the design to each antenna that the return loss was less than -10dB and the axial ratio was less than 3dB. The gain of the antennas was 6.08dBi for a single patch antenna, 9.69dBi for a $2{\times}1$ array antenna, 12.99dBi for a $2{\times}2$ array antenna, 15.72dBi for a $2{\times}4$ array antenna and 18.39dBi for a $4{\times}4$ array antenna. When the elements of the array antenna were increased, it was confirmed that it increased by about 3dBi.

Identification of 2D Impulse Response by use of M-array with Application to 2D M-transform

  • Liu, Min;Kashiwagi, Hiroshi;Kobatake, Hidefumi
    • 제어로봇시스템학회:학술대회논문집
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    • 1999.10a
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    • pp.234-237
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    • 1999
  • In this paper, a new method for identification of two-dimensional(2D) impulse response is presented. As is well known, identification of 2D impulse response is an important and necessary theme for image processing or signal processing. Here, the authors extend M-transform which has been proposed by some of the authors to 2D case where an image is used instead of signal, and M-array is used instead of M-sequence. Firstly, we show that 2D impulse response can be obtained by use of M-array. Next 2D M-transform is defined where any 2D image can be considered to be the output of 2D filter whose input is 2D M-array. Simulation results show the effectiveness of identification of 2D impulse response by either using M-array or by 2D M-transform.

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New systolic arrays for computation of the 1-D and 2-D discrete wavelet transform (1차원 및 2차원 이산 웨이브렛 변환 계산을 위한 새로운 시스톨릭 어레이)

  • 반성범;박래홍
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.34S no.10
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    • pp.132-140
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    • 1997
  • This paper proposes systolic array architectures for compuataion of the 1-D and 2-D discrete wavelet transform (DWT). The proposed systolic array for compuataion of the 1-D DWT consists of L processing element (PE) arrays, where the PE array denotes the systolic array for computation of the one level DWT. The proposed PE array computes only the product terms that are required for further computation and the outputs of low and high frequency filters are computed in alternate clock cycles. Therefore, the proposed architecuter can compute the low and high frequency outputs using a single architecture. The proposed systolic array for computation of the 2-D DWT consists of two systolic array architectures for comutation of the 1-D DWT and memory unit. The required time and hardware cost of the proposed systolic arrays are comparable to those of the conventional architectures. However, the conventional architectures need extra processing units whereas the proposed architectures fo not. The proposed architectures can be applied to subband decomposition by simply changing the filter coefficients.

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Interpolation Technique for 3-D Conformal Array (3차원 콘포멀 어레이에서의 인터폴레이션 기술의 적용)

  • Kang, Kyung-mook;Seol, Kyung-Eun;Jeon, Junghwan;Koh, Jinhwan
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.41 no.12
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    • pp.1748-1751
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    • 2016
  • In this correspondence, we studied 3D uniform rectangular array as an extension of interpolation technique to compensate the beam pattern of 3D conformal array. The simulation result shows outstanding performance comparing to 2D interpolations.

Implementation of systolic array for 2-D IIR digital filters (2-D IIR digital filter에 대한 systolic array구현)

  • 김수현
    • Proceedings of the Acoustical Society of Korea Conference
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    • 1992.06a
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    • pp.29-32
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    • 1992
  • In this paper, a systolic array structure is derived from the realization of 2-D IIR digital filters directed from the SFG(signal flow graph). After realized the 1-D formed partial systolic array, we implemented the complete systolic array to be cascaded 1-D form. The cascading of partial systolic arrays reduce the storage element which sued to delay input signal. 1-D systolic array is derived from that DG is designed through local communication approach and then it mapping to SFG. The derived structure is very simple and has high throughput because during new imput sample is supplied, new output is obtained every sampling period. And broadcast input signal is eliminated. Since the systolic array has property of regularity, modularity, local interconnection and highly synchronized multiprocessing, thus is very suitable for VLSI implementation.

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A unified systeolic array for computation of the 2D DCT/DST/DHT (2D DCT/DST/DHT 계산을 위한 단일화된 시스톨릭 어레이)

  • 반성범;박래홍
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.33B no.2
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    • pp.103-110
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    • 1996
  • In this paper, we propose a unified systolic array for the computation of the 2D discrete cosine transform/discrete sine transform/discrete hartley transform (DCT/DST/DHT). The unified systeolic array for the 2D DCT/DST/DHT is a generalization of the unified systolic array for the 1D DCT/DST/DHT. In order to calculate the 2D transform, we compute 1D transforms along the row, transpose them, and obtain 1D transforms along the column. When we compare the proposed systolic array with the conventional method, our architecture exhibits a lot of advantages in terms of latency, throughput, and the number of PE's. The simulation results using very high speed integrated circuit hardware description language (VHDL), international standard language for hardware description, show the functional validity of the proposed architecture.

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Design of an Optimal Planar Array Structure with Uniform Spacing for Side-Lobe Reduction

  • Bae, Ji-Hoon;Seong, Nak-Seon;Pyo, Cheol-Sig;Park, Jae-Ick;Chae, Jong-Suk
    • Journal of electromagnetic engineering and science
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    • v.3 no.1
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    • pp.17-21
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    • 2003
  • In this paper, we design an optimal planar array geometry for maximum side-lobe reduction. The concept of thinned array is applied to obtain an optimal two dimensional(2-D) planar array structure. First, a 2-D rectangular array with uniform spacing is used as an initial planar array structure. Next, we modify the initial planar array geometry with the aid of thinned array theory in order to reduce the maximum side-lobe level. This is implemented by a genetic algorithm under some constraint, minimizing the maximum side-lobe level of the 2-D planar array. It is shown that the optimized planar array structure can achieve low side-lobe level without optimizing the excitations of the array antennas.

Side Lobe Level Improvement Using a 1:2:2:1 Non-Uniformly Excited Sub-Array (1:2:2:1 비균등 부배열을 이용한 부엽 레벨 개선)

  • Jung, Jinwoo;Kim, Jaesin;Han, Duk-Chan
    • Journal of the Korea Institute of Military Science and Technology
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    • v.20 no.1
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    • pp.90-97
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    • 2017
  • In this paper, we propose a new array antenna scheme which has an improved side lobe level (SLL) as well as a simplified feeding network and a high gain. The proposed array scheme is based on a non-uniformly excited sub-array. For analysis, we use an array factor of sub-array antenna. In the simulation results, the simulated SLL and gain provide more than 18.43 dB and 26.63 dBi, respectively. For the verification of the proposed design scheme, the prototype antenna with $16{\times}8$ radiating elements was designed by the proposed array scheme. The measured SLL and gain are more than 19.85 dB and 25.53 dBi, respectively. This measurement result indicates that the proposed array scheme is reasonable.

A Study on Optimization of Structure for Hexagon Tile Sub-array Antenna System (Hexagon 타일 부배열 안테나 시스템 구조 최적화에 관한 연구)

  • Jung, Jinwoo;Pyo, Seongmin
    • Journal of IKEEE
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    • v.26 no.1
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    • pp.129-132
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    • 2022
  • In this paper, a technique for optimizing the sub-array system structure that can minimize the side lobe level of the phased-array antenna is proposed. Optimization of the proposed array antenna structure is to adjust the spacing between sub-arrays and sub-arrays by using a hexagonal array structure of one sub-array and a hexagonal sub-array for six hexagonal arrays, and thus the entire phased array antenna system of the radiation pattern was optimized. Compared to the 2-dimensional planar antenna system, the proposed technique maintains a gain of 24.3 dBi and a half-power beam-width of 8.46 degrees without change, and only reduces -3.4 dB and -6.5 dB in the x-axis and y-axis directions, respectively.