• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.4
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• pp.24-29
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• 1983

In this paper, a floating-point processor which satisfied the subset of the proposed IEEE standard has been designed and realized by TTL chips. This processor consists of a floating-point arithmetic unit and a control sequencer. AHPL has been used in the design of sequencer. The execution times for the arithmetic operations were measured and compared with other microprocessor. The results had shown faster operations compared to the Z-80 processor. Though this processor was built by TTL chips, it could be fabricated as a one-chip processor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8B
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• pp.1532-1539
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• 1999

In this paper, we propose a bit synchronizer which is suitable for frequency hopping systems. The proposed bit synchronizer is an ADPLL in which the digial loop filter is combined with an error symbol detecting circuit using an adaptive window. Suppressing the tracking process when hop mute and impulse noises are detected improves the performance of the digital loop filter and enhances the probability of the frequency hopping system. The simulation results demonstrate an improved performance of the proposed bit synchronizer compared with existing ones.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.59-65
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• 1999

In this paper, we design a entorpy encoder of HDTV/DTV encoder blocks on the basis of MPEG-II. The designed entropy encoder outputs its bit stream at 9Mbps bit rate inserting zero-stepping block to protect the depletion of buffer in case that the generated bit stream is stored in buffer and uses not only PROM bit combinational circuit to solve the problem of critical path, and packer block, one of submerge, is designed to packing into 24 bit unit using barrel shifter, and it is constructed to blocks of header information encoder, input information delay, submerge, and buffer control. Designed circuits is verified by VHDL function simulation, as a result of performing P&R with Gate compiler that apply $0.8{\mu}m$ Gate Array specification, pin and gate number of total circuits has been tested to each 235 and about 120,000.

• Journal of the Korea Society of Computer and Information
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• v.24 no.11
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• pp.21-27
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• 2019

Recently, embedded systems have been introduced in various fields such as smart factories, industrial drones, and medical robots. Since sensor data collection and IoT functions for machine learning and big data processing are essential in embedded systems, it is essential to port the operating system that is suitable for the function requirements. However, in embedded systems, it is necessary to separate the hard real-time system, which must process within a fixed time according to service characteristics, and the flexible real-time system, which is more flexible in processing time. It is difficult to port the operating system to a low-performance embedded device such as 8BIT MCU to perform simultaneous real-time. When porting a real-time OS (RTOS) to a low-specification MCU and performing a number of tasks, the performance of the real-time and general processing greatly deteriorates, causing a problem of re-designing the hardware and software if a hard real-time system is required for an operating system ported to a low-performance MCU such as an 8BIT MCU. Research on the technology that can process real-time processing system requirements on RTOS (ported in low-performance MCU) is needed.

• Journal of IKEEE
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• v.24 no.4
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• pp.1058-1063
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• 2020

This paper proposes a 12-bit SAR A/D(Successive Approximation Register Analog-to-Digital) converter that operates at low power for bio-signal and sensor signal processing. The conventional SAR A/D converter utilized the reduction of the dynamic current, which resulted in reducing total power consumption. In order to solve the limitation of the sampling time due to charging/discharging of the capacitor for reducing dynamic current, the different sampling time on the C-DAC bit switch operation was applied to reduce the dynamic current. In addition, lowering the supply voltage of the digital block to 0.6V led to 70% reduction of the total power consumption of the proposed ADC. The proposed SAR A/D was implemented with CMOS 65nm process 1-poly 6-metal, operates with a supply voltage of 1.2V. The simulation results demonstrate that ENOB, DNL/INL, power consumption and FoM are 10.4 bits, ±0.5LSB./±1.2LSB, 31.2uW and 2.8fJ/step, respectively.

• The Magazine of the IEIE
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• v.12 no.3
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• pp.15-21
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• 1985

• Journal of Korean Electronics
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• v.24 no.4
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• pp.34-36
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• 2004

• Journal of Korean Electronics
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• v.24 no.8
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• pp.9-11
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• 2004

• Journal of Biomedical Engineering Research
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• v.25 no.1
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• pp.43-47
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• 2004

Interests in human brain functionality and its connectivity have much frown up. DTI (Diffusion tensor imaging) has been known as a non-invasive MR) technique capable of providing information on water diffusion in tissues and the organization of white matter tract. Thus. It can provide us the information on the direction of brain fiber tract and the connectivity among many important cortical regions which can not be examined by other anatomical or functional MRI techniques. In this study. was used the 24 bit color coding scheme on the IDL platform in the windows environment to visualize the orientation of major fiber tracts of brain such as main association, projection, commissural fibers and corticospinal tracts. We additionally implemented a color coding scheme for each directional component and FA (fractional anisotropy), and used various color tables for them to be visualized more definitely. Consequently we implemented a fancy and basic technique to visualize the directional information of fiber tracts efficiently and we confirmed the feasibility of the 24 bit color coding scheme in DTI by visualizing main fiber tracts.

• Journal of IKEEE
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• v.24 no.3
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• pp.814-820
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• 2020

In the M-ary DCSK system up to now, as M increases, the distance between constellation signal points becomes closer and performance deteriorates. we propose a hybrid modulation scheme based on PPM and DCSK to improve the BER performance. one part of the bit is modulated by the PPM and the other part by DCSK. Thus, the information bearing signal is modulated simultaneously according to the selected pulse position of the PPM determined by the information bit and the additional information bit. The analytical BER performance of the proposed plan is derived and verified by simulation. The results show that the proposed scheme outperforms conventional M-DCSK, code index modulation DCSK and rectified code index DCSK in additional white Gaussian noise and multipath Rayleigh fading channels.