• The Journal of Information Technology
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• v.6 no.3
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• pp.65-73
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• 2003

The evaluation AP embedded Linux board is implemented. The board is made of IBM 405 GP processor, PPCBoot-1.2.1 boot loader, Linux-2.4.21 kernel and root file system. The evaluation board has two flash memories, boot flash and application flash of size 512Kbyte and 16Mbyte, respectively. And it supports IEEE 802.11a which provide the maximum throughput of 54Mbps in the 5.2GHz frequency band. MTD(Memory Technology Device) and JFFS2(Journalling Flash File System version 2) technologies are adopted to optimally package the system software, boot loader, kernel and root file system. And in order to optimize root file system, busybox package and tiny login are used. Linux kernel and root file system is combined together with mkimage utility.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.4
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• pp.484-491
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• 2008

In this paper, we design and fabricate the L-band high speed pulsed HPA using LDMOS FET. And we propose the high voltage and high speed switching circuit for LDMOS FET. The pulsed HPA using LDMOS FET is simpler than using GaAs FET because it has a high gain, high output power and sin81e voltage supply. LDMOS FET is suitable for pulsed HPA using switching method because it has $2{\sim}3$ times higher maximum drain-source voltage(65 V) than operating drain-source voltage($V_{ds}=26{\sim}28\;V$). As results of test, the output peak power is 100 W at 1.2 GHz, the rise/fall time of output RF pulse are 28.1 ns/26.6 ns at 2 us pulse width with 40 kHz PRF, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.500-505
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• 2002

In this paper, a novel architecture of programmable divider with fifty percent duty cycle output and programmable dividing number has been proposed. Through HSPICE simulation, a 900MHz frequency synthesizer with proposed frequency divider has designed in a standard 0.25$\mu\textrm{m}$ CMOS technology. To verify the operation of proposed frequency divider, a chip had been fabricated using 0.65$\mu\textrm{m}$ 2-poly, 3-metal standard CMOS processing and experimental result shows that the proposed frequency divider works well. The designed voltage controlled oscillator(VCO) has a center frequency of 900MHz, a tuning range of ${\pm}$10%, and a gain of 154MHz/V. The simulated frequency synthesizer performance has a settling time of 1.5${\mu}\textrm{s}$, a frequency range from 820MHz to 1GHz and power consumption of 70mW at 2.5V power supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.3
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• pp.227-247
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• 2015

An X-band $8{\times}16$ dual-polarized active phased array antenna system has been implemented based on the substrate integrated waveguide(SIW) technology having low propagation loss, complete EM shielding, and high power handling characteristics. Compared with the microstrip case, 1 dB less is the measured insertion loss(0.65 dB) of the 16-way SIW power distribution network and doubled(3 dB improved) is the measured radiation efficiency(73 %) of the SIW sub-array($1{\times}16$) antenna element. These significant improvements of the power division loss and the radiation efficiency using the SIW, save more than 30 % of the total power consumption, in the active phased array antenna systems, through substantial reduction of the maximum output power(P1 dB) of the high power amplifiers. Using the X-band $8{\times}16$ dual-polarized active phased array antenna system fabricated by the SIW technology, the main radiation beam has been steered by 0, 5, 9, and 18 degrees in the accuracy of 2 degree maximum deviation by simply generating the theoretical control vectors. Performing thermal cycle and vacuum tests, we have found that the SIW array antenna system be eligible for the space environment qualification. We expect that the high efficiency SIW array antenna system be very effective for high performance radar systems, massive MIMO for 5G mobile systems, and various millimeter-wave systems(60 GHz WPAN, 77 GHz automotive radars, high speed digital transmission systems).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.7
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• pp.771-777
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• 2008

In this paper, a frequency doubler using modified time-delay technique is proposed. A voltage controlled delay line (VCDL) in the proposed frequency doubler compensates the group delay time mismatching between input and delayed signal. With the group delay time matching and waveform shaping using the adjustable Schmitt triggers, the unwanted fundamental component($f_0$) and the higher order harmonics such as third and fourth are diminished excellently. In result, only the doubled frequency component($2f_0$) appears dominantly at the output port. The frequency doubler is designed at 1.15 GHz of $f_0$ and fabricated with TSMC $0.18\;{\mu}m$ CMOS process. The measured output power at $2f_0$ is 2.67 dBm when the input power is 0 dBm. The obtained suppression ratio of $f_0,\;3f_0$, and $4f_0$ to $2f_0$ are 43.65, 38.65 and 35.59 dB, respectively.

• Journal of the Korean Ceramic Society
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• v.43 no.6 s.289
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• pp.338-343
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• 2006

The effects of lead-borosilicate glass frits on the sintering behavior and microwave dielectric properties of ceramic-glass composites were investigated as functions of glass composition of glass addition ($10{\sim}50vol%$), softening point (Ts) of the glass, and sintering temperature of the composites ($500{\sim}900^{\circ}C$ for 2 h). The addition of 50 vol% glass ensured successful sintering below $900^{\circ}C$. Sintering characteristics of the composites were well described in terms of Ts. PbO addition in to the glass enhanced the reaction with $Al_{2}O_3$ to form liquid phase and $PbAl_{2}Si_{2}O_8$, which was responsible to lower Ts. Dielectric constant(${\epsilon}_r$), $Q{\times}f_0$ and temperature coefficient of resonant frequency (${\tau}_f$) of the composite with 50 vol% glass contents ($B_{2}O_{3}:PbO:SiO_{2}:CaO:Al_{2}O_3$ = 5:40:45:5:5) demonstrated 8.5, 6,000 GHz, $-70\;ppm/^{\circ}C$, respectively, which is applicable to substrate requiring a low dielectric constant. When the same glass composition was applied sinter $MgTiO_3\;and\;TiO_2,\;at\;900^{\circ}C$ (50 vol% glass in total), the properties were 23.8, 4,000 GHz, $-65ppm/^{\circ}C$ and 31.1, 2,500 GHz, $+80ppm/^{\circ}C$ respectively, which is applicable to filter requiring an intermidiate dielectric constant.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.437-444
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• 2015

A high output power voltage controlled oscillator (VCO) in the U-band was implemented using a 65 nm CMOS process. The proposed VCO used a transmission line to increase output voltage swing and overcome the limitations of CMOS technologies. Two varactor banks were used for fine tuning with a 5% frequency tuning range. The proposed VCO showed small variation in output voltage and operated at 51.55-54.18 GHz. The measured phase noises were -51.53 dBc/Hz, -91.84 dBc/Hz, and -101.07 dBc/Hz at offset frequencies of 10 kHz, 1 MHz, and 10 MHz, respectively, with stable output power. The chip area, including the output buffer, is $0.16{\times}0.16mm^2$ and the maximum output power was -0.11 dBm. The power consumption was 33.4 mW with a supply voltage of 1.2-V. The measured $FOM_P$ was -190.8 dBc/Hz.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.4
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• pp.25-31
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• 2017

This paper presents a 270/540/750/1500-Mb/s serial-data transmitter realized in a $0.13-{\mu}m$ CMOS technology for the applications of video data transmission. A low-cost RG-58 copper cable(5C-HFBT-RG6T) is exploited as a transmission medium connected to a single BNC connector, which shows cable loss 45 dB in maximum at 1.5 GHz. RLGC modeling provides an equivalent circuit for SPICE simulations of which characteristics are very similar to the measured cable loss. The loss can be compensated by pre-emphasis at transmitter and equalization at receiver if needed. Measurements of the proposed transmitter chip demonstrate the operations of 270-Mb/s, 540-Mb/s, 750-Mb/s and 1.5-Gb/s, and provide the output voltage levels of $370mV_{pp}$ at 1.5 Gb/s even with the pre-emphasis turned-off. The total power consumption is 104 mW from 1.2/3.3-V supplies and the chip occupies the area of $1.65{\times}0.9mm^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.54-61
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• 2016

A 6-Gbps single-ended receiver with a linear equalizer and a self-reference generator is proposed for a high-speed interface with the double data rate. The proposed single-ended receiver uses a common gate amplifier to increase a voltage gain for an input signal with low voltage level. The continuous-time linear equalizer which reduces gain to the low frequencies and achieves high-frequency peaking gain is implemented in the common gate amplifier. Furthermore, a self-reference generator, which is controlled with the resolution 2.1 mV using digital averaging method, is implemented to maximize the voltage margin by removing the offset noise of the common gate amplifier. The proposed single-ended receiver is designed using a 65-nm CMOS process with 1.2-V supply and consumes the power of 15 mW at the data rate of 6 Gbps. The peaking gain in the frequency of 3 GHz of the designed equalizer is more than 5 dB compared to that in the low frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.4
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• pp.805-810
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• 2014

In this paper, the characteristics of a series-fed dipole pair antenna with an end-aligned strip pair director are studied. In the proposed SDP antenna, two strip dipole antennas with different lengths and a ground reflector are connected trough a coplanar stripline. The strip pair director placed above the second dipole element are two rectangular-shaped strips and is aligned at the ends of the two arms of the second dipole. The variations on the antenna performance for different lengths and widths of the director are analyzed, and optimal design parameters for the enhancement of the bandwidth are obtained. The optimized SDP antenna is fabricated on an FR4 substrate, and the experimental results show that the antenna has a frequency band of 1.65-2.95 GHz for a VSWR < 2, which shows enhanced bandwidth compared to the conventional SDP antenna.