• Journal of the Microelectronics and Packaging Society
• /
• v.29 no.4
• /
• pp.1-8
• /
• 2022

High-density packaging technologies, including Through-Si-Via (TSV) technologies, are considered important in many fields such as IoT (internet of things), 6G/5G (generation) communication, and high-performance computing (HPC). Achieving high integration in two dimensional packaging has confronted with physical limitations, and hence various studies have been performed for the three-dimensional (3D) packaging technologies. In this review, we described about the causes and effects of scallop formation in TSV, the scallop-free etching technique for creating smooth sidewalls, Cu pillar and Cu-SiO₂ hybrid bonding in TSV. These technologies are expected to have effects on the formation of high-quality TSVs and the development of 3D packaging technologies.

• Journal of the Semiconductor & Display Technology
• /
• v.22 no.4
• /
• pp.38-47
• /
• 2023

Three dimensional (3D) packaging is a next-generation packaging technology that vertically stacks chips such as memory devices. The necessity of 3D packaging is driven by the increasing demand for smaller, high-performance electronic devices (HPC, AI, HBM). Also, it facilitates innovative applications across another fields. With growing demand for high-performance devices, companies of semiconductor fields are trying advanced packaging techniques, including 2.5D and 3D packaging, MR-MUF, and hybrid bonding. These techniques are essential for achieving higher chip integration, but challenges in mass production and fine-pitch bump connectivity persist. Advanced bonding technologies are important for advancing the semiconductor industry. In this review, it was described 3D packaging technologies for chip integration including mass reflow, thermal compression bonding, laser assisted bonding, hybrid bonding.

• Journal of the Microelectronics and Packaging Society
• /
• v.30 no.3
• /
• pp.11-19
• /
• 2023

Recently with the rapid advancement of artificial intelligence (AI) technologies such as Chat GPT, AI semiconductors have become important. AI technologies require the ability to process large volumes of data quickly, as they perform tasks such as big data processing, deep learning, and algorithms. However, AI semiconductors encounter challenges with excessive power consumption and data bottlenecks during the processing of large-scale data. Thus, the latest packaging technologies are required for AI semiconductor computations. In this study, the authors have described packaging technologies applicable to AI semiconductors, including interposers, Through-Silicon-Via (TSV), bumping, Chiplet, and hybrid bonding. These technologies are expected to contribute to enhance the power efficiency and processing speed of AI semiconductors.

• Journal of the Optical Society of Korea
• /
• v.18 no.5
• /
• pp.531-537
• /
• 2014

Through-silicon vias (TSVs) are fine, deep holes fabricated for connecting vertically stacked wafers during three-dimensional packaging of semiconductors. Measurement of the TSV geometry is very important because TSVs that are not manufactured as designed can cause many problems, and measuring the critical dimension (CD) of TSVs becomes more and more important, along with depth measurement. Applying white-light scanning interferometry to TSV measurement, especially the bottom CD measurement, is difficult due to the attenuation of light around the edge of the bottom of the hole when using a low numerical aperture. In this paper we propose and demonstrate four bottom CD measurement methods for TSVs: the cross section method, profile analysis method, tomographic image analysis method, and the two-dimensional Gaussian fitting method. To verify and demonstrate these methods, a practical TSV sample with a high aspect ratio of 11.2 is prepared and tested. The results from the proposed measurement methods using white-light scanning interferometry are compared to results from scanning electron microscope (SEM) measurements. The accuracy is highest for the cross section method, with an error of 3.5%, while a relative repeatability of 3.2% is achieved by the two-dimensional Gaussian fitting method.

• Journal of the Microelectronics and Packaging Society
• /
• v.21 no.4
• /
• pp.91-96
• /
• 2014

Through silicon via (TSV) technology is to form a via hole in a silicon chip, and to stack the chips vertically for three-dimensional (3D) electronics packaging technology. This can reduce current path, power consumption and response time. In this study, Cu-filling substrate size was changed from Si-chip to a 4" wafer to investigate the behavior of Cu filling in wafer level. The electrolyte for Cu filling consisted of $CuSO_4$ $5H_2O$, $H_2SO_4$ and small amount of additives. The anode was Pt, and cathode was changed from $0.5{\times}0.5cm^2$ to 4" wafer. As experimental results, in the case of $5{\times}5cm^2$ Si chip, suitable distance of electrodes was 4cm having 100% filling ratio. The distance of 0~0.5 cm from current supplying location showed 100% filling ratio, and distance of 4.5~5 cm showed 95%. It was confirmed good TSV filling was achieved by plating for 2.5 hrs.

• Korean Journal of Metals and Materials
• /
• v.49 no.5
• /
• pp.388-394
• /
• 2011

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.

• Journal of the Microelectronics and Packaging Society
• /
• v.28 no.1
• /
• pp.61-66
• /
• 2021

SnO2 has the wide bandgap which allows it to be used as the photocatalyst. There are many studies to enhance the photocatalytic properties of SnO2. In this study, 3-dimensional SnO2 aerogel was synthesized using epoxide-initiated sol-gel method for the optimal specific surface area. Also, graphene oxide (GO) was added before the gelation process of the aerogel to maximize the specific surface area. Addition of 0.5 wt% of GO would possibly enhance the specific surface area by 1.7 times compared with the bare tin oxide aerogel. Furthermore, enhanced specific surface area could degrade 67.3% of initial Rhodamine B in 120 minutes. To compare with the bare SnO2 aerogel, 0.5 wt% GO addition to SnO2 could double the reaction rate of the photocatalytic degradation.

• Journal of the Microelectronics and Packaging Society
• /
• v.17 no.3
• /
• pp.79-84
• /
• 2010

Formation of TSV (Through-Si-Via) with an Au seed layer and Cu filling to the via, simplification of bumping process for three dimensional stacking of Si dice were investigated. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process using $SF_6$ and $C_4F_8$ plasmas alternately. The vias were 40 ${\mu}m$ in diameter, 80 ${\mu}m$ in depth, and were produced by etching for 1.92 ks. On the via side wall, a dielectric layer of $SiO_2$ was formed by thermal oxidation, and an adhesion layer of Ti, and a seed layer of Au were applied by sputtering. Electroplating with pulsed DC was applied to fill the via holes with Cu. The plating condition was at a forward pulse current density of 1000 mA/$dm^2$ for 5 s and a reverse pulse current density of 190 mA/$dm^2$ for 25 s. By using these parameters, sound Cu filling was obtained in the vias with a total plating time of 57.6 ks. Sn bumping was performed on the Cu plugs without lithography process. The bumps were produced on the Si die successfully by the simplified process without serious defect.

• Journal of the Ergonomics Society of Korea
• /
• v.25 no.2
• /
• pp.85-94
• /
• 2006

The purpose of this study is to extract typical body shapes of Korean adults based on the three-dimensional Korean anthropometric data measured through 5th national anthropometric survey and to examine the suitability of the 3-D human shape data for the interior packaging. 36 three-dimensional anthropometric variables related to the design of vehicle interior were considered for the appraisal of typical body shapes. Four major factors were extracted by the factor analysis and factor scores were calculated for all subjects. Typical or standard drivers of Korean adults were selected by the minimum deviation criteria for the four factor scores with respect to 5th, 50th, and 95th percentiles, respectively. Typical drivers of Korean adults were visualized by the CATIA-HUMAN program due to the absence of proper application software for three-dimensionally scanned human body data. There are considerable differences between the anthropometric data of Korean adults and those provided by CATIA-HUMAN program, which shows that the modeling data provided by CATIA-HUMAN should not be directly applied to the ergonomic evaluation for the vehicle design. This suggests the necessity for the development of suitable software for scanned human shape data. It is also expected that the anthropometric data of typical drivers extracted from this study help design package layouts and improve the suitability of ergonomic evaluation for Korean customers.

• KOREAN JOURNAL OF PACKAGING SCIENCE & TECHNOLOGY
• /
• v.19 no.2
• /
• pp.61-65
• /
• 2013

Modified atmosphere (MA) of reduced $O_2$ and elevated $CO_2$ concentrations has been used for keeping the quality of fresh produce and extending the shelf life. As a way to attain the beneficial MA package around the produce, a gas diffusion tube or perforation can be attached onto the container and controlled on real time in its opening/closing responding to $O_2$ and $CO_2$ concentrations measured by gas sensors. The timely-controlled opening of the gas diffusion tube can work in harmony with the produce respiration and help to create the desired MA. By use of the mathematical modeling, the effect of tube dimension on the controlled container atmosphere was figured out in this study. Spinach and king oyster mushroom were used as typical commodities for designing the model container system (0.35 and 0.9 kg in 13 L, respectively) because of their respiration characteristics and the optimal MA condition ($O_2$ 7~10%/$CO_2$ 5~10% for spinach; $O_2$ 2~5%/$CO_2$ 10~15% for mushroom). With a control logic for the gas composition to stay as close as possible to optimum MA window without invading injurious low $O_2$ and/or high $CO_2$ concentrations, the atmosphere of the sensor-controlled container could stay at its lower $O_2$ boundary or upper $CO_2$ limit under certain tube dimensional conditions. There were found to be the ranges of the tube diameter and length allowing the beneficial MA. The desired range of the tube dimension for spinach consisted of combinations of larger diameter and shorter length in the window of 0.3~2 cm diameter and 0.2~10 cm length. Similarly, that for king oyster mushroom was combinations of larger diameter and shorter length in the window of 0.9~2 cm diameter and 0.2~3 cm in length. Clear picture on generally affordable tube dimension range may be formulated by further study on a wide variety of commodity and pack conditions.