• The Journal of the Acoustical Society of Korea
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• v.30 no.2
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• pp.107-113
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• 2011

This paper describes a development of a loop filter design in a physical modeling of the plucked string instrument. The conventional method proposed by V$\"{a}$lim$\"{a}$ki cannot estimate right parameters if a sound has either very short sustain or no sustain. In order to overcome this drawback, we propose the use of the decay region and 5 to 20 harmonics of the sound in the estimation of loop filter parameters. The most appropriate filter coefficient is chosen by frequency signal to noise ratio. To verify the performance of the proposed method, the guitar, gayageum and geomungo were selected as the target because they have different shape, structure, and material of strings. Regardless of the duration of harmonics, the proposed method was able to estimate the loop filter parameters representing frequency-dependent damping of harmonics.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.6
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• pp.550-557
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• 2003

In this paper, two dualband internal antennas for GPS/PCS handset are proposed. At first, the monopole antenna with parasitic dipole element is designed to print PCB of handset directly. At second, the antenna with bended loop structure is designed to bend to use internal space of handset maximumly. The proposed dualband internal antennas provide a 2:1 VSWR bandwidth of over 19.1 % which are possible to cover two bands at once. the antennas have a gain between -0.4 and 3.33 ㏈i at all bands and they have almost omni-directional patterns.

• Journal of international Conference on Electrical Machines and Systems
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• v.1 no.2
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• pp.79-84
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• 2012

In this paper, a three-phase high-voltage converter (HVC), in which the main structure of each phase is composed of a cascaded PWM rectifier (CPR) and cascaded inverter (CI), is studied. A high-voltage grid is the input of the HVC. In order to ensure proper operation of the HVC, the control method should achieve output voltage sharing (OVS) among the rectifiers in the CPR, OVS among the inverters in the CI, and high power factor. Master-slave direct-current control (MDCC) is used to control the CPR. The ability of the control system to prevent interference is strong when using MDCC. The CI is controlled by three-loop control, which is composed of an outer common-output-voltage loop, inner current loops and voltage sharing loops. Simulation results show low total harmonic distortion (THD) in the HVC input currents and good OVS in both the CPR and CI.

• Transactions on Electrical and Electronic Materials
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• v.18 no.2
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• pp.103-110
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• 2017

The number of applications of solar photovoltaic (PV) systems in power generation grids has increased in the last decade because of their ability to generate efficient and reliable power in a variety of low installation in domestic applications. Various PV converter topologies have therefore emerged, among which the modular multilevel converter (MMC) is very attractive due to its modularity and transformerless features. The modeling and control of the MMC has become an interesting issue due to the extremely large expansion of PV power plants at the residential scale and due to the power quality requirement of this application. This paper proposes a novel control method of MMC which is used to directly integrate the photovoltaic arrays with the power grid. Traditionally, a closed loop control has been used, although circulating current control and capacitors voltage balancing in each individual leg have remained unsolved problem. In this paper, the integration of model predictive control (MPC) and traditional closed loop control is proposed to control the MMC structure in a PV grid tied mode. Simulation results demonstrate the efficiency and effectiveness of the proposed control model.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.2
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• pp.46-52
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• 2014

This paper presents a multiple gain controlled digital phase and frequency detector with a fast lock-time. Lock-time of the digital PLL can be significantly reduced by applying proposed adaptive gain control technique. A loop gain of the proposed digital PLL is controlled by three conditions that are very large phase difference between reference and feedback signal, small phase difference and before lock-state, and after lock-state. The simulation result shows that lock-time of the proposed multiple gain controlled digital PLL is 100 times faster than that of the conventional structure with unit gain mode.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.11
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• pp.1280-1287
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• 2012

The 3.2~6.5 GHz wideband YTO(YIG Tuned Oscillator) module is designed, fabricated and measured. To improve the phase noise characteristic of the YTO module, offset PLL(Phase Locked Loop) structure with sampling mixer is applied. This YTO module is composed of sampling mixer, phase detector, loop filter, current driver, and YTO. The phase noise of the fabricated YTO module is measured as -100 dBc/Hz at 10 kHz offset frequency, which approximates the predicted result at the center frequency of 4.5 GHz. This YTO module presents over 10 dB improved phase noise compared to conventional PLL module from operating frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.5
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• pp.515-525
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• 2014

In this paper, we present a design and implementation of a Voltage-tuned Planar Composite Resonator Oscillator(Vt-PCRO) with a low phase noise. The designed Vt-PCRO is composed of a resonator, two phase shifters, and an amplifier. The resonator is designed using a dual mode SIW(Substrate Integrated Waveguide) resonator and has a group delay of about 40 nsec. Of the two phase shifters (PS1 and PS2), PS1 with a phase shift of $360^{\circ}$ is used for the open loop gain to satisfy oscillation condition without regard to the electrical lengths of the employed microstrip lines in the loop. PS2 with a phase shift of about $70^{\circ}$ is used to tune oscillation frequency. The amplifier is constructed using two stages to compensate for the loss of the open loop. Through the measurement of the open loop gain, the tune voltage of the PS1 can be set to satisfy the oscillation condition and the loop is then closed to form the oscillator. The oscillator with a oscillation frequency of 5.345 GHz shows a phase noise of -130.5 dBc/Hz at 100 kHz frequency offset. The oscillation power and the electrical frequency tuning range is about 3.5 dBm and about 4.2 MHz for a tuning voltage of 0~10 V, respectively.

• Molecules and Cells
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• v.43 no.12
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• pp.1035-1045
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• 2020

The Drosophila genome contains four low molecular weight-protein tyrosine phosphatase (LMW-PTP) members: Primo-1, Primo-2, CG14297, and CG31469. The lack of intensive biochemical analysis has limited our understanding of these proteins. Primo-1 and CG31469 were previously classified as pseudophosphatases, but CG31469 was also suggested to be a putative protein arginine phosphatase. Herein, we present the crystal structures of CG31469 and Primo-1, which are the first Drosophila LMW-PTP structures. Structural analysis showed that the two proteins adopt the typical LMW-PTP fold and have a canonically arranged P-loop. Intriguingly, while Primo-1 is presumed to be a canonical LMW-PTP, CG31469 is unique as it contains a threonine residue at the fifth position of the P-loop motif instead of highly conserved isoleucine and a characteristically narrow active site pocket, which should facilitate the accommodation of phosphoarginine. Subsequent biochemical analysis revealed that Primo-1 and CG31469 are enzymatically active on phosphotyrosine and phosphoarginine, respectively, refuting their classification as pseudophosphatases. Collectively, we provide structural and biochemical data on two Drosophila proteins: Primo-1, the canonical LMW-PTP protein, and CG31469, the first investigated eukaryotic protein arginine phosphatase. We named CG31469 as DARP, which stands for Drosophila ARginine Phosphatase.

• Journal of international Conference on Electrical Machines and Systems
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• v.1 no.2
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• pp.85-90
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• 2012

This paper presents a topology structure and control method for an input-parallel-output-series(IPOS) inverter system which is suitable for high input current, high output voltage, and high power applications. In order to ensure the normal operation of the IPOS inverter system, the control method should achieve input current sharing(ICS) and output voltage sharing(OVS) among constituent modules. Through the analysis in this paper, ICS is automatically achieved as long as OVS is controlled. The IPOS inverter system is controlled by a three-loop control system which is composed of an outer common-output voltage loop, inner current loops and voltage sharing loops. Simulation results show that this control strategy can achieve low total harmonic distortion(THD) in the system output voltage, fast dynamic response, and good output voltage sharing performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.181-187
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• 2003

This paper presents an 125MHz, 128-phase phase-locked loop using interpolation technique for digital timing recovery. To reduce the power consumption and chip area, phase interpolation was performed over only selected windows, instead of overall period. Four clocks were used for phase interpolation to avoid the output jitter increase due to the interpolation clock (clock used for phase interpolation) switching. Also, the output clock was fed back to finite-state machine (FSM) where the multiplexer selection signals are generated to eliminate the possible output glitches. The PLL implemented in a $0.25\mu\textrm{m}$ CMOS process and dissipates 80mW at 2.5V supply and occupies $0.84\textrm{mm}^2.