• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.11
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• pp.1082-1089
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• 2004

In this paper, miniaturization of an elliptic-response open-loop resonator filter and design flexibility using similarity transformation of the coupling matrix are proposed. Moreover, the filter with wider fractional bandwidth is designed by the proposed method. In order to verify the proposed method, three 4th-order elliptic-response open-loop resonator filters with a relative bandwidth of 4 % at the center frequency of 2.0 GHz are designed. One is realized with constant-width microstrip line resonator and the others are implemented with different-width microstrip line resonator. Compared with the former one, the latter have shown the size reduction of 13 % and 25 %, respectively. Since it may not be possible to implement the resonators with very narrow spacing for the required coupling coefficient filters with two different configurations representing same response characteristic through similarity transformation of the coupling matrix are proposed. From this design flexibility, a filter with a relative bandwidth of 8 % at the center frequency of 2.0 GHz is designed with realizable design parameters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1774-1781
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• 1997

In this paper, we propose a full digital frequency and phase locked loop for CATV and HDTV receivers adopting VSB modulation. The CATV and HDTV receivers proposed by the Grand-Alliance in USA are ultilizing analog signal processing technology for carrier recovery. By the way, it is not a good architecture for the development of single chip ASIC operating in digital domain. To solve this problem while improving the performance, we first down convert the received r.f. signal to a near baseband signal for a low-rate AD converter and then we use digital signal processing techniques. The proposed system has the frequency pull-in range of -200 KHz +2.50 KHz. Moreover, it has the ability of adaptive loop bandwidth control according to the amount of frequency offset to improve the acquisition time while reducing the phase noise.

• Geophysics and Geophysical Exploration
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• v.6 no.4
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• pp.187-194
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• 2003

A small-loop electromagnetic (EM) system using multiple frequencies has advantages in survey speed and cost despite of limitation on its depth of investigation. Therefore, small-loop EM surveys have been frequently used on various site investigations involving engineering and environmental problems. We have developed a subsurface imaging technique using small loop EM data. We used a one-dimensional (ID) inversion method to reconstruct a subsurface image from frequency EM sounding data. Tests using simulated data show that the method can reasonably recover the subsurface resistivity structure. Also, the method was tested on field data obtained with multiple frequency small loop EM system at a farm in Chunchon, Korea. The resistivity image obtained form field data compares favorably with the image from the dipole-dipole resistivity survey.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6A
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• pp.685-692
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• 2008

In this paper, we propose a timing recovery loop for Inmarsat mini-m system downlink receiver. Inmarsat mini-m system requires a timing recovery loop which is robust in frequency offset and has fast acquisition because Inmarsat mini-m system specification requires frequency tolerance is required of ${\pm}924$ Hz (signal bandwidth: 2.4 kHz) and acquisition time of UW (Unique Word) signal duration (15ms).Therefore, we propose a timing recovery loop which is suitable for Inmarsat mini-m system. The proposed timing recovery loop adopted noncoherent UW detector and differential ELD which applied differential UW signal for stability and fast acquisition in frequency offset environment. Simulation results show that the proposed timing recovery loop has stable operation and fast acquisition in frequency offset environment for the system.

• The Journal of the Acoustical Society of Korea
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• v.30 no.2
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• pp.107-113
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• 2011

This paper describes a development of a loop filter design in a physical modeling of the plucked string instrument. The conventional method proposed by V$\"{a}$lim$\"{a}$ki cannot estimate right parameters if a sound has either very short sustain or no sustain. In order to overcome this drawback, we propose the use of the decay region and 5 to 20 harmonics of the sound in the estimation of loop filter parameters. The most appropriate filter coefficient is chosen by frequency signal to noise ratio. To verify the performance of the proposed method, the guitar, gayageum and geomungo were selected as the target because they have different shape, structure, and material of strings. Regardless of the duration of harmonics, the proposed method was able to estimate the loop filter parameters representing frequency-dependent damping of harmonics.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.12
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• pp.84-89
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• 2010

In this paper, a novel voltage-controlled oscillator (VCO) using the microstrip square open loop dual split ring resonator is presented for reducing the phase noise. The square-shaped dual split ring resonator having the form of the microstrip square open loop is investigated to reduce the phase noise. Compared with the microstrip square open loop resonator and the microstrip square open loop split ring resonator as well as the conventional microstrip line resonator, the microstrip square dual split ring resonator has the larger coupling coefficient value, which makes a higher Q value, and has reduced the phase noise of VCO. The VCO with 1.7V power supply has the phase noise of -123.2~-122.0 dBc/Hz @ 100 kHz in the tuning range, 11.74~11.75 GHz. The figure of merit (FOM) of this VCO is-214.8~-221.7 dBc/Hz dBc/Hz @ 100 kHz in the same tuning range. Compared with VCO using the conventional microstrip line resonator, VCO using microstrip square open loop resonator, the phase noise of VCO using the proposed resonator has been improved in 26 dB, 10 dB, respectively.

• Journal of the Korea institute for structural maintenance and inspection
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• v.23 no.1
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• pp.85-93
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• 2019

Structural performance and serviceability of precast deck system are mostly determined by connection details between precast decks. Particularly, since the bridge deck is under repeated loads such as traffic loads, fatigue behavior and performance of joints should be investigated. In this study, a two-girder continuous composite bridge specimen was fabricated using the asymmetric ribbed loop joints, and static and fatigue load tests were conducted to evaluate the structural behavior and the crack pattern of the bridge deck. From the test results, the proposed precast deck system resulted in sufficient fatigue performance and failure strength. Therefore, the proposed precast deck system can be applied to the connection part of precast decks effectively.

• Korean Journal of Optics and Photonics
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• v.11 no.3
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• pp.163-165
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• 2000

We propose a new structure of optical cross connect based on a WDM MUX/DEMUX pair and switchable mirrors. In experiment, we demonstrate the operation of the optical cross connect using an optical fiber loop mirror connected to a $2\times2$ optical switch as a switchable mirror.mirror.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.21-31
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• 2010

This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.122-133
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• 2013

An arbiter-based simple phase decision circuit (PDC) optimized for high-resolution phase-to-digital converter made up of an analog phase-frequency detector and a time-to-digital converter for all-digital phase-locked loops is proposed. It can distinguish very small phase difference between two pulses even though it consumes lower power and has smaller input-to-output delay than the previously reported PDC. Proposed PDC is realized using 130-nm CMOS process and demonstrated by transistor-level simulations. A 5-bit P2D having no offset nor deadzone using the PDC is also demonstrated. A harmonic-lock-free and small-phase-offset delay-locked loop for fixing the P2D resolution regardless of PVT variations is also proposed and demonstrated.