• Journal of the Optical Society of Korea
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• v.9 no.3
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• pp.119-122
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• 2005

Silica-based $2\times2$ thermo-optic (TO) switch using the MMI couplers which have a large fabrication tolerance of 110 (${\mu}m$ were fabricated and operated. Important features of the proposed switch are shown to be a polarization dependency loss of 0.1dB, an extinction ratio of 32.7dB, and a power consumption of 202.8mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1245-1251
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• 1999

A 1.25Gb/s path control switch chip has been designed and implemented with COMPASS tool and 0.8${\mu}{\textrm}{m}$ CMOS gate-array of LG semiconductor. This device controls the path of digital singnals in SDH-based transmission system. The proposed switch chip is suitable for self-healing operations both in a linear network and an unidirectonal ring, The self-healing operation of the switch is effectively done by the configuration information stored in the resisters of the switch. The test device adapted to SDH-based transmission system, show immediate restoration and a 10-11~10-12 bit error raito. And 2.5Gb/s or more high throughput can be realized by combining rwo identical or more switches with the parallel architecture.

• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• Journal of the Korea Society of Computer and Information
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• v.7 no.2
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• pp.115-123
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• 2002

This thesis proposes a new type of Input-Output Buffered ATM Switch which employs an arbiter and its performance under different traffic conditions studied. The proposed switch is designed with a view to exploit the architecture and other characteristics of the arbiter. The primary aim of the proposed switch is the elimination, or at least, the reduction of HOL blocking phenomenon which occurs in the simple input buffered switch. Several HOL arbitration algorithms have been proposed for this purpose in the literature. The proposed switch attempts to reduce the HOL blocking as it uses the arbiter and the buffer at the output port in an effective manner. The arbiter is designed to work with Three Phase Algorithm which is one of the many well known HOL arbitration algorithms. The Proposed switch acquires control over priority transmission through the REQ signal. As the signals are transmitted to the arbiter, the latter controls the one which is sent by the input buffer. Computer simulation results have been provided to demonstrate the effectiveness of the Proposed switch under uniform traffic conditions.

• Journal of the Korea Society of Computer and Information
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• v.8 no.2
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• pp.97-105
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• 2003

This thesis proposes a new type of Input-Output Buffered ATM Switch which employs an arbiter and its performance under different traffic conditions studied. The proposed switch is designed with a view to exploit the architecture and other characteristics of the arbiter The primary aim of the proposed switch is the elimination, or at least, the reduction of HOL blocking phenomenon which occurs in the simple input buffered switch. Several HOL arbitration algorithms have been proposed for this purpose in the literature. The Proposed switch attempts to reduce the HOL blocking as it uses the arbiter and the buffer at the output Port in an effective manner. The arbiter is designed to work with Three Phase Algorithm which is one of the many well known HOL arbitration algorithms . The proposed switch acquires control over priority transmission through the REd signal. As the signals are transmitted to the arbiter, the latter controls the one which is sent by the input buffer. Computer simulation results have been provided to demonstrate the effectiveness of the proposed switch under non-uniform random traffic conditions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.1926-1940
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• 1998

This paper is the part II of research results on the performance evaluation of fully interconnected ATM switch, and includes the performance evaluation results for bursty traffic and nonuniform distribution. The switch model is a fyully interconnected switch type proposed by ETRI and is the proper architecutre for a small-sized switch element. The proposed switch consists of two steps of buffering scheme in the switch fabric in order to effectively absorb the effect of bursty nature of ATM traffic. The switch uses bit addressing method for addressing shcmeme and thus it is easy to implement multicasting function without adding additional functional block. In order to incorporate the bursty nature of traffic in ATM networks, we use IBP(Interrupted Bernoulli Process) model as an input traffic model as well as random traffic model which has been used as a traditional traffic model. In order to design the various scenarios for simulation, we considered both uniform and nonuniform output distribution, and also implemented multicast function. In this paper, we presented the simulation results in diverse environments and evaluated the performance of the switch.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.12
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• pp.679-684
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• 2000

Closing switch, key component of pulsed power system, is constructed simply and used frequently due to the easy control and manufacture of one. The kind of one are spark-gap, triggered vacuum switch, pseudo-spark switch and INPIStron. But the electrode of spark gap switch is damaged with the hot spot by Z-pinch and then the life of one become short. INPIStron with inverse pinch effect has long life but it is difficult trigger system to provide uniform discharge between cathode and anode. In this paper, the design and manufacturing of INPIStron with gas puffing trigger method in order to supply uniform discharge inter-electrode and the performance of the developed INPIStron applied to 500[kA]-2[MJ] pulsed power system is presented.

• Transactions on Electrical and Electronic Materials
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• v.14 no.3
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• pp.116-120
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• 2013

This paper proposes a novel RF MEMS dc-contact switch with stiff membrane on a quartz substrate. The uniqueness of this work lies in the utilization of a seesaw mechanism to restore the movable part to its rest position. The switching action is done by using separate pull-down and pull-up electrodes, and hence operation of the switch does not rely on the elastic recovery force of the membrane. One of the main problems faced by electrostatically actuated MEMS switches is the high operational voltages, which results from bending of the membrane, due to internal stress gradient. This is resolved by using a stiff and thick membrane. This membrane consists of flexible meanders, for easy movement between the two states. The device operates with an actuation voltage of 6.43 V, an insertion loss of -0.047 dB and isolation of -51.82 dB at 2 GHz.

• The KIPS Transactions:PartC
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• v.8C no.4
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• pp.389-396
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• 2001

기존의 라우터 기반의 패킷 스크리닝 방식은 ATM 네트워크 상에서는 패킷 수준의 스크리닝 기능의 적용을 위하여 SAR(Segmentation And Reassembly) 과정을 필요로 하기 때문에 고속의 셀 처리를 수행하는 ATM Switch의 셀 처리 속도를 저하시킨다는 문제점을 안고 있다. 본 논문에서는 셀 스크리닝 방식에 기반한 병렬 처리 구조의 ATM Firewall Switch를 제안한다. 제안된 Enhanced ATM Firewall Switch는 셀 단위로 분할된 패킷의 1, 2번 셀들에 대한 검사만을 통하여 스크리닝 기능을 수행하기 때문에 셀 단위의 스크리닝 수행이 가능하며, 정책 캐쉬의 도입을 통해 셀 스크리닝 수행속도를 향상하였다. 또한 독립적인 User Cells Filter 기능 블록의 설계를 통하여 병렬 처리 구조의 셀 스크리닝 수행이 가능하도록 구성하여 셀 지연 시간을 최소화하였다.

• Proceedings of the KIEE Conference
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• 2003.07e
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• pp.158-161
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• 2003

A new soft switching technique that improves performance of the high power factor boost rectifier by reducing switching losses is introduced. The losses are reduced by air active snubber which consists of an inductor, a capacitor a rectifier, and an auxiliary switch. Since the boost switch turns off with zero current, this technique is well suited for implementations with insulated gate bipolar transistors. The reverse recovery related losses of the rectifier are also reduced by the snubber inductor which is connected in series with the boost switch and the boost rectifier. In addition, the auxiliary switch operates with zero voltage switching. A complete design procedure and extensive performance evaluation of the proposed active snubber using a 1.2[kW] high power factor boost rectifier operating from a $90[V_{rms}]$ input are also presented.