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Transform-Limited Optical Short Pulse Generation by Compression of Gain-Switched DFB Laser Pulses (DFB 레이저 이득 스위칭과 펄스 압축을 이용한 변환 제한된 초단 광 펄스 발생)

  • 조성대;이창희;신상영;채창준
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.35D no.6
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    • pp.92-98
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    • 1998
  • The transform limited optical short pulses are generated by compression of pulses from a gain switched distributed feedback laser at 5 GHz repetition rate. The gain-switched pulses have the minimum pulse width of 27 psec with the spectral width of 1.1 nm. Thus the output pulses have a large amount of linear chirp and nonlinear chirp. We suppress the nonlinear chirp by passing the pulses through the optical band pass filter with 3 dB band width of 0.55 nm which is narrower than spectral width of the input pulses and generate 7.1 psec pulses by compressing the output with the dispersion compensating fiber. The pulses have time-bandwidth product of 0.49 which is close to the transform limited gaussian pulse. These pulses can be utilized as optical sources in 40 Gbit/s time division multiplexed optical transmission system.

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A Wide - Range Dual-Loop DLL with Programmable Skew - Calibration Circuitry for Post Package (패키지후 프로그램을 이용 스큐 수정이 가능한 광범위한 잠금 범위를 가지고 있는 이중 연산 DLL 회로)

  • Choi, Sung-Il;Moon, Gyu;Wee, Jae-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.6
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    • pp.408-420
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    • 2003
  • This paper describes a Delay Locked Loop (DLL) circuit having two advancements : 1) a dual loop operation for a wide lock-range and 2) programmable replica delays using antifuse circuitry and internal voltage generator for a post-package skew calibration. The dual loop operation uses information from the initial time-difference between reference clock and internal clock to select one of the differential internal loops. This increases the lock-range of the DLL to the lower frequency. In addition, incorporation with the programmable replica delay using antifuse circuitry and internal voltage generator allows for the elimination of skews between external clock and internal clock that occur from on and off-chip variations after the package process. The proposed DLL, fabricated on 0.16m process, operates over the wide range of 42MHz - 400MHz with 2.3v power supply. The measured results show 43psec peak-to-peak jitter and 4.71psec ms jitter consuming 52㎽ at 400MHz.

A Study on the Defect Annealing of Hafnium Metal By Positron Annihilation Techniques (양전자소멸기법을 이용한 하프늄금속의 격자결함 회복에 관한 연구)

  • Kang, Myung-Soo;Jung, Sung-Hoon;Yoon, Young-Ku;Park, Yong-Ki
    • Nuclear Engineering and Technology
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    • v.25 no.1
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    • pp.71-79
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    • 1993
  • Positron annihilation characteristics and microhardness of 25% cold worked and isochronally annealed hafnium specimens were measured to study recovery and recrystallization stages of hafnium specimens. The annihilation lifetime of positrons in hafnium has been measured for the distinct cases of annihilation in the annealed lattice and annihilation after trapping at lattice defects generated by cold deformation at room temperature. The annihilation lifetime in the annealed lattice was 187 $\pm$3.7 psec, whereas it was 217 $\pm$ 4.2 psec for positrons trapped at deformation-induced defects (mostly dislocations). The changes in Doppler broadening and hardness showed similar trend in the recrystallization range, however, the measured value of Doppler broadening variation were quite sensitive to changes in the recovery region in which the variation in hardness value was completely insensitive. Recovery of cold worked hafnium initiated at about 623 K and recrystallization occurred at around 1023 K.

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Capacitive compensation and consequent bandwidth expansion of 2.5 Gbps optical transmitter module (2.5Gbps 광송신 모듈의 용량선 보상 및 대역폭 확대)

  • 김성일;김상배;이해영
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.7
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    • pp.216-222
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    • 1996
  • Since many typical 2.5 Gbps optical transmitter modules use a 50$\Omega$ characteristic impedance, they require relatively high voltage and high power sources compared to the 25$\Omega$ module. However, simple replacement of the 50$\Omega$ internal matching impedance with 25$\Omega$ results in bandwidth reduction and consequent problem of data transmitter module is proposed in order to expand the modulator bandwidth. From the calculated resutls based on accurate 3-dimensional inductance analysis, we have found that the series parasitic inductance is a dominant element limiting the bandwidth and the insertion of a 2.5pF capacitor in parallel to the 20$\Omega$ matching resiter can increase the 3 dB bandwidth about 1.4GHz wider. The time-domain results show the rise time (140 psec) without the compensation is greatly improved to 63 psec with the compensation. This capacitive ocmpensation can be implemented easily and be compatible with common manufacturing process of the optical transmitter module.

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Phase-Locked Loop with Leakage and Power/Ground Noise Compensation in 32nm Technology

  • Kim, Kyung-Ki;Kim, Yong-Bin;Lee, Young-Jun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.7 no.4
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    • pp.241-246
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    • 2007
  • This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 $M{\sim}725$ MHz with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

Optical pulse parameter analysis of gain switched InGaAIP FP LD at 650 nm wavelegth and its characteristic in comparison with CW operation (이득스위칭을 이용한 650nm InGaAIP FP LD의 광펄스 파라메터 분석 및 CW 발진과의 특성비교)

  • 오광환;채정혜;이용탁;백운출;김덕영
    • Korean Journal of Optics and Photonics
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    • v.12 no.2
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    • pp.135-142
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    • 2001
  • Recently, plastic optical fiber draws a lot of attention as a new transmission medium for local area network (LAN) and home network applications. As PMMA based GI-POF (Graded Index Plastic Optical Fiber) has very low loss at about 500 nm and 650 nm wavelengths, it is very important to have a compact ultra short optical pulse source at these wavelength windows. In this paper, we have investigated detailed characteristics of gain switched laser system by using a commercially available low cost RF devices and an InGaAlP Fabry Perot semiconductor laser operating at 650 nm wavelength. The shortest optical 'pulse obtained was 33 psec with 1 GHz repetition rate. Depending on the DC bias current and the modulation frequency, the FWHM and the pulse energy of the gain switched pulses show 33.3-82.8 psec and 0.97-9.69 pI respectively. Also, the spectral bandwidths for CW and gain switched operations are 0.44 nm and 1.50 nm. We believe that these results are quite useful for high bit rate optical transmission applications with PMMA based plastic optical fibers in addition to estimate properties of ultra fast optical components and electro-optic devices. vices.

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Implementation and miniaturization of High Order Derivative Gaussian Pulse Generator for DS-UWB (DS-UWB를 위한 고차 미분 가우시안 펄스 생성기의 소형화와 구현)

  • Kim, Dong-Ho;Bang, Gyeong-Nam;Park, Chong-Dae
    • Journal of IKEEE
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    • v.10 no.2 s.19
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    • pp.109-115
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    • 2006
  • In this paper, High order derivative Gaussian pulse generator for DS-UWB communication satisfying the regulation of FCC was proposed and fabricated. In order to transform rectangular signal of 100Mbps to a Gaussian pulse, the fabricated Gaussian pulse generator consists of only two SRD. The output pulse had the widths of 330 psec and amplitudes of 920 mV. In addition, the designed and fabricated dual bandpass filter shows high order derivate characteristics by using micro-strip line and parallel stub to remove WLAN band. We generated the 13th Gaussian pulse restricted frequency spectrum of WLAN band more than -25dB. The pulse had pulse width of 1 nsec and amplitude of 25 mV.

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A high-resolution synchronous mirror delay using successive approximation register (연속 근사 레지스터를 이용한 고정밀도 동기 미러 지연 소자)

  • 성기혁;김이섭
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.10
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    • pp.63-68
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    • 2004
  • A high-resolution synchronous mirror delay (SMD) is proposed in order to reduce the clock skew between the external clock and the infernal clock of a chip. The proposed SMD reduces the clock skew in two steps. Coarse locking is achieved by the SMD. Fine locking is achieved by the successive approximation register-controlled DLL. The total locking time is 10 clock cycles. Simulation results show that the proposed SMD operates with 50psec clock skew at 182MHz and consumes 17.5mW at 3.3V supply voltage in a 0.35 um 1-poly 4-metal CMOS technology.

A Novel Clock Distribution Scheme for High Performance System and A Structural Analysis of Coplanar and Microstrip Transmission Line (고성능 시스템을 위한 클록 분배 방식 및 Coplanar 및 Microstrip 전송라인의 구조적 분석)

  • Park, Jung-Keun;Moon, Gyu;Wee, Jae-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.4
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    • pp.1-8
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    • 2004
  • A novol clock distribution scheme is proposed for high-speed and low-power digital system to minimize clock skew and reduce dynamic power consumption. This scheme has ideal zero-skew characteristic by using folded clock lines (FCL) and phase blending circuit. For analyzing suitable line structures to FCLs, microstrip line and coplanar line are placed with folded clock lines. Simulation results show that the maximum clock-skew between two receivers located 10mm apart is less than lops at 1㎓ and the maximum clock-skew between two receivers located 20mm apart is less than 60ps at 1㎓. Also the results show that the minimum skews of clock signals regardless of process, voltage, and temperature variation are invariant.

Design of Impulse generator Using Gain-Switched Semiconductor Laser for UWB (반도체 레이저의 이득스위칭을 이용한 UWB 임펄스 발생기 설계)

  • Kwon Soon-young;Kim Bum-in;Park Chong-dae
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.42 no.6 s.336
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    • pp.61-66
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    • 2005
  • In this paper, we implemented a impulse generator, the one of the part in UWB(Ultra Wide Band) system using step recovery diode(SRD) and gain-switced semiconductor laser. The impulse generator was consisted of four stages; The first stage used SRD to generate the first impulse for gain switching. The second stage controled current for the suitable gain switching condition. The third was the second impulse generator to generate gaussian pulse. For gain switching, the first impulse was applied to semiconductor laser. In the last stage the gain switched impulse was converted into mono-gaussian pulse. The measured mono-gaussian pulse was 360 psec pulse-width and $-70mV \~ +50mV$ amplitude in time domain. In frequency domain its magnitude and bandwidth was, respectively, -41dBm and 3.6GHz. Accordingly, the impulse generator that we suggested was suitable for UWB systems.