• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.3C
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• pp.240-246
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• 2008

An MPEG-2/4 AAC decoder on 16-bit fixed-point processor is presented in this paper. To meet audio quality criteria, despite small word length, special design methods for 16-bit foxed-point AAC decoder were devised. This paper presents particular algorithms for 16-bit AAC decoding. We have implemented an efficient AAC decoder using the proposed algorithms. Audio contents can be replayed in the decoder without quality degradation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6A
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• pp.593-602
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• 2006

This paper propose to methodology for deciding suitable bit size that minimizes hardware complexity and performance degradation from floating-point design the fixed-point implementation of downlink traffic channel of IEEE 802.16e OFDMA TDD system. One of the major considering issues for implementing fixed-point design is to select Saturation or Quantization properly with the knowledge of signal distribution by pdf or histogram. Also, through trial and error, we should execute exhaustive computer simulation for various bit sizes, hence obtain appropriate bit size while minimizing performance degradation. We carry out computer simulation to decide the optimized bit size of downlink traffic channel under AWGN and ITU-R M.1225 Veh-A channel model.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.7C
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• pp.735-742
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• 2006

In this paper, we explain the operation scheme and fixed-point design method of DFE (Digital Front End), which performs DC offset compensation, automatic frequency control, and automatic gain control over the input signal to the UE (User Equipment) receiver of IEEE 802.16e OFDMA-TDD system. Then, we analyze the performance of DFE under ITU-R M. 1225 Veh-A 60km/h channel environment. To optimize the fixed-point design of DFE, we reduce the number of bit resulted from calculation without performance degradation, leading to the decreased complexity of the operation in H/W, and design the Loop filter with considering trade-off between the Acquisition time and the Stability.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.2
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• pp.37-43
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• 2009

In this study, multi-channel digital hearing aid algorithm for low power system is proposed. First, MDCT(Modified Discrete Cosine Transform) method converts time domain of input speech signal into frequency domain of it. Output signal from MDCT makes a group about each channel, and then each channel signal adjusts a gain using LCF(Loudness Compensation Function) table depending on hearing loss of an auditory person. Finally, compensation signal is composed by TDAC and IMDCT. Its all of process make progress 16-bit fixed-point operation. We use fast-MDCT instead of MDCT for reducing system complexity and previously computed tables instead of log computation for estimating a gain. This algorithm evaluate through computer simulation.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1295-1297
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• 1996

CCITT G.721, G.723 standard ADPCM algorithm is implemented by using TI's fixed point DSP start kit (DSK). ADPCM can be implemented on a various rates, such as 16K, 24K, 32K and 40K. The ADPCM is sample based compression technique and its complexity is not so high as the other speech compression techniques such as CELP, VSELP and GSM, etc. ADPCM is widely applicable to most of the low cost speech compression application and they are tapeless answering machine, simultaneous voice and fax modem, digital phone, etc. TMS320C50 DSP is a low cost fixed point DSP chip and C50 DSK system has an AIC (analog interface chip) which operates as a single chip A/D and D/A converter with 14 bit resolution, C50 DSP chip with on-chip memory of 10K and RS232C interface module. ADPCM C code is compiled by TI C50 C-compiler and implemented on the DSK on-chip memory. Speech signal input is converted into 14 bit linear PCM data and encoded into ADPCM data and the data is sent to PC through RS232C. The ADPCM data on PC is received by the DSK through RS232C and then decoded to generate the 14 bit linear PCM data and converted into the speech signal. The DSK system has audio in/out jack and we can input and out the speech signal.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1257-1260
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• 2005

This paper is related to optimization in the image data format, which can make a great effect in performance of data compression and is based on the wavelet transform and JPEG2000. This paper established a criterion to decide the data format to be used in wavelet transform, which is on the bases of the data errors in frequency transform and quantization. This criterion has been used to extract the optimal data format experimentally. The result were (1, 9) of 10-bit fixed-point format for filter coefficients and (9, 7) of 16-bit fixed-point data format for wavelet coefficients and their optimality was confirmed.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.399-402
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• 2004

This paper presents a system-on-chip prototype implementing a full integration for a portable digital audio system. The chip is composed of a audio processor block to implements audio decoding and voice compression or decompression software, a system control block including 8-bit MCU core and Memory Management Unit (MMU) a low power 16-bit ${\Sigma}{\Delta}$ CODEC, two DC-to-BC converter, and a flash memory controller. In order to support other audio algorithms except Mask ROM type's fixed codes, a novel 16-bit fixed-point DSP core with the program-download architecture is proposed. Funker, an efficient power management technique such as task-based clock management is implemented to reduce power consumption for portable application. The proposed chip has been fabricated with a 4 metal 0.25um CMOS technology and the chip area is about 7.1 mm ${\times}$ 7.1mm with 100mW power dissipation at 2.5V power supply.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1211-1214
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• 1998

Real-time implementation of Conjugate-Structure Algebraic CELP(CS-ACELP) is presented. ITU-T Study Group(SG) 15 has standardized the CS-ACELP speech coding algorithm as G.729. A real-time implementation of the CS-ACELP is achieved using 16 bit fixed point DSP16210 Digital Signal Processor (DSP) of Lucent Technologies. The speech coder has been implemented in the bit-exact manner using the fixed point CS-ACELP C source which is the part of the G.729 standard. To provide a multi-channel vocoder solution to digital communication system, we try to minimize the complexity(e.g., MIPS, ROM, RAM) of CS-ACELP. Our speech coder shows 15.5 MIPS in performance which enables 4 channel CS-ACELP to be processed with one DSP16210.

• The Journal of the Acoustical Society of Korea
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• v.19 no.4
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• pp.45-51
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• 2000

This paper describes real-time implementation of a multi-channel G.729A speech coder using a 16 bit fixed-point Digital Signal Processor (DSP) and its application to a Voice Mailing Service (VMS) system. TMS320C549 by Texas Instruments was used as a fixed point DSP chip and a 4 channel G.729A coder was implemented on the chip. The implemented coder required 14.5 MIPS for the encoder and 3.6 MIPS for the decoder at each channel. In addition, memories required by the coder were 9.88K words and 1.69K words for code and data sections, respectively. As a result, the developed VMS system that accommodates two DSP chips was able to support totally 8 channels. Experimental results showed that the our multi-channel coder passes all of test vectors provided by ITU-T.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.859-862
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• 1999

We designed a 128-tap FIR filter for a modem which complies with ITU-T V.32. We adopted pipeline technique and realized delay-taps with two ring-buffers. The multiplier in this filter carries out 2's complement fixed-point multiplication of 14bit $\times$ 16bit. The designed filter is expected to operate at 50MHz.