• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1985.10a
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• pp.144-147
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• 1985

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.2 s.314
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• pp.39-45
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• 2007

This paper presents a novel scheme that quickly searches for the sweet spot of multiple array antennas, and locks on to it for high-speed millimeter wavelength transmissions, when communications to another antenna array are disconnected. The proposed method utilizes a modified genetic algorithm, which selects a superior initial group through preprocessing in order to solve the local solution in agenetic algorithm. TDD (Time Division Duplex) is utilized as the transfer method and data controller for the antenna. Once the initial communication is completed for the specific number of individuals, no longer antenna's data will be transmitted until each station processes GA in order to produce the next generation. After reproduction, individuals of the next generation become the data, and communication between each station is made again. Simulation results of 1:1, 1:2, 1:5 array antennas confirmed the efficiency of the proposed method. The 16bit split is 8bit, but it has similar performance as 16bit gene.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.1
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• pp.109-114
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• 2017

In this study, we have developed the active leakage current detection module based on a MSP430 processor, 16bit signal processor. This module can be operated in a desired trip threshold within 0.03 seconds as specified in KS C 4613. This developed module is expected to be applicable as a module for prevention of electric shock in smart distribution panel of smart grid.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.341-345
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• 1996

This paper presents the dynamics and the teal-time control of a horizontally rotating inverted pendulum. The dynamic equations representing three degrees of freedom rigid body motion of the pendulum are derived, and the state feedback controller is applied to the motion control of the pendulum. A 32 bit counter board with 16 bit hardware communication ability is developed to improve the real-time control performance and is applied to a horizontally rotating inverted pendulum. The simulation and experimental studies are conducted to evaluate the performance of the developed pendulum system and the timing in the real-time control is analyzed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.717-720
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• 2007

This paper presents a novel scheme that quickly searches for the optimal direction of multiple directional antennas, and locks on to it for high-speed millimeter wavelength transmissions, when communications to another antenna directional are disconnected. The proposed method utilizes a modified genetic algorithm, which selects a superior initial group through preprocessing in order to solve the local solution in genetic algorithm. TDD (Time Division Duplex) is utilized as the transfer method and data controller for the antenna. Once the initial communication is completed for the specific number of individuals, no longer antenna's data will be transmitted nil each station processes GA in order to produce the next generation. After reproduction, individuals of the next generation become the data, and communication between each station is made again. In order to verify the effectiveness of the proposed system, simulation results of 1:1, 1:2, 1:5 directional antennas and experiment results of 1:1 directionalantennas confirmed the efficiency of the proposed method. The 16bit split is 8bit, but it has similar performance as 16bit gene.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.1
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• pp.53-59
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• 2009

By the use of open source and 16bit Microcomputer, IDB(Integrated Development Board) for embedded technical education was designed and developed. Based on 16bit MCU H8/300H, LED, LED Matrix, motors, sensors and various I/O circuitry, and the connection to a computer via the SCI, and $16{\times}2$ character LCD was designed and implemented on IDB. In addition, the software development environment was build by the assembler and H8 C compiler which is provided to the open-source software. And memory expansion was considered to include TRON(Real time OS) and uClinux. To verify the developed board, IDB was fabricated by PCB machine, and the fuction was confirmed by the basic I/O control program.

• Journal of IKEEE
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• v.21 no.3
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• pp.185-194
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• 2017

In this paper, a modular platform for wearable devices is proposed which can be easily assembled by exchanging functions according to various field and environment conditions. The proposed modular platform consists of a 32-bit RISC CPU, a 32-bit symmetric multi-core processor, and a 16-bit DSP. It also includes a plug & play features which can quickly respond to various environments. The sensing and communication modules are connected in the form of a chain. This work is implemented in a standard 130 nm CMOS technology and the proposed modular wearable platforms are verified with temperature and humidity sensors.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.8
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• pp.671-677
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• 2016

A Controller Area Network (CAN) is a serial communication protocol that is highly reliable and efficient in many aspects, such as wiring cost and space, system flexibility, and network maintenance. Therefore, it is chosen for the communication protocol between a single chip controller based on Field Programmable Gate Array (FPGA) and peripheral devices. In this paper, the design and implementation of CAN IP, which is written in VHSIC Hardware Description Language (VHDL), is presented. The implemented CAN IP is based on the CAN 2.0A specification. The CAN IP consists of three processes: clock generator, bit timing, and bit streaming. The clock generator process generates a time quantum clock. The bit timing process does synchronization, receives bits from the Rx port, and transmits bits to the Tx port. The bit streaming process generates a bit stream, which is made from a message received from a micro controller subsystem, receives a bit stream from the bit timing process, and handles errors depending on the state of the CAN node and CAN message fields. The implemented CAN IP is synthesized and downloaded into SmartFusion FPGA. Simulations using ModelSim and chip test results show that the implemented CAN IP conforms to the CAN 2.0A specification.

• Transactions on Electrical and Electronic Materials
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• v.11 no.5
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• pp.238-241
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• 2010

The purpose of this study is to solve the problems of radio frequency bandwidth frequency depletion, confusion possibilities, and security that are in current wireless communications systems, and to confirm the possibility of applying those solutions for the next generation network. To solve the problems of the current wireless communications system, a visible light communications system for power line communication (PLC) via 8-bit microcontroller is created and the capacity is analyzed. The exclusive PLC chip APLC-485MA, an 8-bit ATmega16 microcontroller, high brightness 5pi light emitting diodes (LEDs), and the LLS08-A1 visible light-receiving sensor were used for the transmitter and receiver. The performance was analyzed using a designed program and an oscilloscope. The voltage change was measured as a function of distance from 10-50 cm. Blue LEDs showed the best performance among the measured LED types, with 0.47 V of voltage loss, but for a distance over 50 cm, precise data was not easy to obtain due to the weak light. To overcome these types of problems, specific values such as the changing conditions and efficiency value relevant to the light emitting parts and the visible light-receiving sensor should be calculated, and continuous study and improvements should also be realized for better communication conditions.

• International Journal of Internet, Broadcasting and Communication
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• v.5 no.2
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• pp.11-14
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• 2013

This paper describes the sigma-delta ADC/DAC digital block with two channels. The ADC block has comb filter and three half band filters. And the DAC block has 5th Cascaded-of-Integrators Feedback DSM. The ADC and DAC support I2S, RJ, LJ and selectable input data modes of 24bit, 20bit, and 16bit. It is fabricated with 0.35um Hynix standard CMOS cell library. The chip size is 3700*3700um. It has been verified using NC Verilog Simulator and Matlab Tool.