• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.4C
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• pp.462-467
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• 2007

This paper proposes Minimum Distance Searching Algorithm (MDSA) which reduces the computational complexity (CC) of the ML, the kind of Spatial Multiplexing (SM) MIMO system. The MDSA searchs candidate symbols with a starting symbol, which is called reference bits. We used the linear receiver of MIMO techniques to find a starting symbol. The MDSA searchs the shortest path to a transmitted symbol using reference bits and Minimum Distance(MD) concept. The CC of MDSA is reduced to the 0.21% to the ML as the transmit antennas is 4 in 16QAM. The simulation result shows the BER of MDSA is nearly same to the BER of ML as the transmit antennas is 2 and the receive antennas is 3 in 16QAM and slightly degraded to the BER of ML as the transmit antennas is 4 and the receive antennas is 6 in QPSK.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.925-931
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• 2008

In video coding standard H.264/AVC, variable block size mode algorithm improves compression efficiency but has need of a large amount of computation for various block modes and mode decision. Meanwhile, decided inter block modes depend on the complexity of a block image, and then the more complex a macroblock is, the smaller its block size is. This paper proposes fast inter block mode decision algorithm. It limits valid block modes to the block modes with a great chance for decision using the image complexity and carries out motion estimation rate-distortion optimization with only the valid block modes. In addition to that, it applies fast motion estimation PDE to the valid block modes with only the $16{\times}16$ block mode. The reference software JM 9.5 was executed to estimate the proposed algorithm's performance. The simulation results showed that the proposed algorithm could save about 24.12% of the averaged motion estimation time while keeping the image quality and the bit rate to be -0.02dB and -0.12% on the average, respectively.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.8-16
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-㎛ column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970×10 ㎛2 and 248 ㎼, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.8 s.338
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• pp.11-16
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• 2005

This paper proposes a bit manipulation accelerator (BMA) having application specific instructions, which efficiently supports scrambling, convolutional encoding, puncturing, and interleaving. Conventional DSPs cannot effectively perform bit manipulation functions since かey have multiply accumulate (MAC) oriented data paths and word-based functions. However, the proposed accelerator can efficiently process bit manipulation functions using parallel shift and Exclusive-OR (XOR) operations and bit jnsertion/extraction operations on multiple data. The proposed BMA has been modeled by VHDL and synthesized using the SEC $0.18\mu m$ standard cell library and the gate count of the BMA is only about 1,700 gates. Performance comparisons show that the number of clock cycles can be reduced about $40\%\sim80\%$ for scrambling, convolutional encoding and interleaving compared with existing DSPs.

• Journal of Korea Multimedia Society
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• v.9 no.10
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• pp.1304-1313
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• 2006

Biometric-based authentication can provide strong security guarantee about the identity of users. However, security of biometric data is particularly important as the compromise of the data will be permanent. In this paper, we propose a secure and efficient protocol to transmit fingerprint images from a fingerprint sensor to a client by exploiting characteristics of fingerprint images. Because the fingerprint sensor is computationally limited, however, such encryption algorithm may not be applied to the full fingerprint images in real-time. To reduce the computational workload on the resource-constrained sensor, we apply the encryption algorithm to a specific bitplane of each pixel of the fingerprint image. We use the LSB as specific bitplane instead of MSB used to encrypt general multimedia contents because simple attacks can reveal the fingerprint ridge information even from the MSB-based encryption. Based on the experimental results, our proposed algorithm can reduce the execution time of the full encryption by a factor of six and guarantee both the integrity and the confidentiality without any leakage of the ridge information.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.336-344
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• 2005

Discrete Wavelet Transform(DWT) is the oncoming generation of compression technique that has been selected for MPEG4 and JEPG2000, because it has no blocking effects and efficiently determines frequency property of temporary time. In this paper, we propose an efficient bit-serial architecture for the low-power and low-complexity DWT filter, employing two-channel QMF(Qudracture Mirror Filter) PR(Perfect Reconstruction) lattice filter. The filter consists of four lattices(filter length=8) and we determine the quantization bit for the coefficients by the fixed-length PSNR(peak-signal-to-noise ratio) analysis and propose the architecture of the bit-serial multiplier with the fixed coefficient. The CSD encoding for the coefficients is adopted to minimize the number of non-zero bits, thus reduces the hardware complexity. The proposed folded 1D DWT architecture processes the other resolution levels during idle periods by decimations and its efficient scheduling is proposed. The proposed architecture requires only flip-flops and full-adders. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a Hynix 0.35$\mu$m STD cell library. The maximum operating frequency is 200MHz and the throughput is 175Mbps with 16 clock latencies.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.9
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• pp.738-745
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• 2012

This paper proposes an approximated soft decision demapping algorithm with low computational complexity for coded 4+12+16 amplitude phase shift keying (APSK) in an additive white Gaussian noise (AWGN) channel. To derive the proposed algorithm, we approximate the decision boundaries for 4+12+16 APSK symbols, and then decide the log likelihood ratio (LLR) value for each bit from the approximated decision boundaries. Although the proposed algorithm shows about 0.6~1.1dB degradation on the error performance compared with the conventional max-log algorithm, it gives a significant result in terms of the computational complexity.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.6
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• pp.109-117
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• 2016

The most important mission of RFID reader is identify EPC (Electronic Product Code) of RFID tag of products that located within distinguishable range of RFID reader. RFID reader transmits query message to RFID tags through wireless channel and RFID tags send unique EPC to response its query message simultaneously. therefore tag collision occurred frequently. RFID tags collision resolution algorithm required to apply RFID technology to various industries. In this paper, we propose enhanced M-ary algorithm that collision bits location is used by not only RFID reader but also tags. the main feature of the proposed algorithm is that integrate multiple query message of M-ary QT algorithm to the single query message by analyze multiple response messages from tags. the simulation results show that the proposed algorithm give better performance than M-ary QT algorithm in terms of the number of query-response, identification efficiency and communication overhead.

• Journal of the Korea Convergence Society
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• v.11 no.6
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• pp.43-49
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• 2020

In spite of the notable advancements of millimeter wave communication technologies, the 60 GHz Wi-Fi is still not widespread yet, mainly due to the high limitation of coverage. Conventionally, it has been hardly possible to support a high data rate with fast beam adaptation while keeping atmospheric beamforming coverage. To solve these challenges in the 60 GHz communication system, holistic system designs are considered. we implemented an enhanced design LDPC decoder enabling 6.72 Gbps coded-throughput with minimal implementation loss, and our proposed phase-tracking algorithm guarantees 3.2 dB performance gain at 1 % PER in the case of 16 QAM modulation and LDPC code-rate 3/4.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.1C
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• pp.14-23
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• 2003

This thesis proposes a sigma-delta modulator architecture with 2 Ms/s data rate and 12 bit resolution. A sigma-delta modulate has the features of oversampling and noise shaping. With these features, it can be connected with low resolution A/D converter to achieve higher resolution A/D converter. Most previous researches have been concentrated on high resolution but low data rate applications, e.g. audio applications. But, in order to be applied to various applications such as wireless data communication, researches on sigma-delta modulator architecture for higher data rate are required. The proposed sigma-delta modulator architecture has the sampling rate of 16 times Nyquist rate to achieve high data rate, and consists of a cascade of two 2nd order sigma-delta modulator to get relatively high resolution. The experimental result shows that the proposed architecture achieves 12-bit resolution at 2 Ms/s data rate.