• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.8
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• pp.784-789
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• 2011

In this paper, a tunable integrated transmitter leakage canceller based on an autotransformer for ultra-high-frequency (UHF) RFID readers is presented. The proposed TX leakage canceller consists of an autotransformer, a digital tuning capacitor, a voltage controlled tuning resistor, and a compensating amplifier, and it is designed using 0.13 ${\mu}m$ 1-poly 6-metal RF CMOS process. The simulation results show that the proposed structure has over 55 dB rejection characteristic between a transmitter and a receiver and a 2.5 dB of the RX insertion loss. The TX leakage canceller can be digitally tuned from 825 MHz to 985 MHz with the tuning capacitor and it can be fully integrated.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.1
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• pp.13-20
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• 2015

Existing LDMOS power amplifier that used class-AB and doherty system shows 55% of efficiency in 60MHz narrow band. Because RRH has been applied to power amplifier at base station. It is required that over 100MHz expanded band and more than 60% high efficiency power amplifier. In this paper we designed class-J power amplifier using LDMOS FET which has over 60% high efficiency characteristic in 200MHz. The output matching circuit of designed class-J power amplifier has been optimized to contain pure reactance at second harmonic load and has low quality factor Q. As a measurement result of the amplifier, when we input continuous wave signal, we checked 62~70% of power added efficiency(PAE) in 2.06~2.2GHz including WCDMA frequency as a 10W class-J power amplifier.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.6
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• pp.613-622
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• 2013

In this paper, an inductive clamping class-E power amplifier has been tested for wireless power transmission at ISM band, 13.56 MHz. The implemented power amplifier is designed to operate stably without destroying power transistor in wireless power transmission system which basically keeps not to align between a transmitting antenna and a receiving antenna. The power amplifier is also designed to enhance harmonic filtering characteristic. The amplifier was tested with a DC supply voltage of 28 V and input power of 25 dBm at 13.56 MHz. The test results show the output power level of 43 dBm, the difference power level between fundamental frequency and second harmonic frequency of more than 55 dBc, the dc current consumption of 830 mA, and the high power-added efficiency of 85 %. Finally, the implemented power amplifier operated normally with 830 mA DC current consumption from 28 V source when the two antennas were aligned, and the power transmission was successful. But when the two antennas were not aligned, its DC current consumption automatically decreased down to 420 mA to protect the switching transistor.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.2
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• pp.162-170
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• 2004

A 900MHz CMOS RF power amplifier with digitally controllable output power has been proposed and designed with 0.6${\mu}{\textrm}{m}$ standard CMOS technology. The designed power amplifier was composed of digitally controllable switch mode pre-amplifiers with an integrated 4nH spiral inductor load and class-C output stage. Especially, to compensate the 1ow Q of integrated spiral inductor, cascode amplifier with a Q-enhancement circuit is used. It has been shown that the proposed power control technique allows the output power to change from almost 3dBm to 13.5dBm. And it has a maximum PAE(Power Added Efficiency) of almost 55％ at 900MHz operating frequency and 3V power supply voltage.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.6
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• pp.55-61
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• 2013

In this paper, we describe design and implementation of audio encoder/decoder for voice synthesis. It uses the encoding of difference value of successive samples instead of the original sample value. and has the compression ratio of 4. The function is verified by using FPGA and the performance is measured by the fabricated chip using $0.35{\mu}m$ standard CMOS process. The system clock is 16.384MHz. The measured THD+n is from -40dB to -80dB with frequency variation and the power consumption is about 80mW. It is suited for the mobile application of high audio quality and low power consumption.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.842-845
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• 2008

This paper propose a dormitory management system based on 13.56MHz RFID system. The proposed dormitory management system consists of three parts, the RFID hardware system the middleware, and the application. RFID hardware system uses 13.56MHz frequency which is suitable for a close range. The middleware is implemented to accept the RFID hardware system values using RS-232c communication method and forward the values to the application. The application is designed to make the DB using the forwarded values, and works based on the DB. The efficacy of the proposed dormitory management system is verified by means of experiments. In the experiments, we set up the system to the dormitory of Daeduk College to show the improvement results of proposed system.

• Electronics and Telecommunications Trends
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• v.13 no.6 s.54
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• pp.46-55
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• 1998

인텔사의 Xeon 프로세서 버스에 정합한 입출력 구동기를 선정하고자, Xeon 프로세서의 구동기술인 AGTL+를 조사하고 AGTL+와 GTL+ 구동기의 혼용 가능성을 분석하였다. GTL+(NTL)을 AGTL+와 함께 사용하고자 할 때 배선 토폴로지, 터미네이션, 댐핑저항 값에 따른 신호 및 시간 특성을 시뮬레이션 하였다. 시뮬레이션의 결과로 80 MHz 이하의 버스속도에서는 Xeon 프로세서 네 개와 GTL+(NTL) 구동기를 혼용하여 안정적으로 동작시킬 수 있음을 보였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.11
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• pp.1574-1579
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• 2016

This paper presents a self-powered sensor-node scheme using a RF wireless power harvesting techniques for improve drone time of flight. Sensor-node that is proposed is turned when two conditions satisfy: The one is input RF ID data from master-node should be same with sensor-node's ID, and the other one is RF wireless power harvesting system is turned on by hysteresis switch. In this paper, master-node's output is 26 dBm at 263 MHz. Maximum RF to DC power conversion efficiency is about 55% at 4-6 dBm input power condition (2 meter from master-node). The maximum RF wireless power harvesting range is about 13 meter form master-node. And power consumption of the sensor-node's load elements such as transmitter, MCU and temperature sensors is approximately average 15 mA at 5.0 V for 10 msec.

• 전자공학회논문지 IE
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• v.45 no.4
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• pp.74-79
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• 2008

The paper represented central management system of dual direction that does opening and shutting, real-time check of various doors of the prison in the on-line network. To remove a fault of 125kHz RFID technology, we use 13.56MHz RFID technology, can solve the problem of the maintenance and trust, development of on-line control and management system that ring the alarm in the abnormal opening and shutting doors.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.48-55
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• 2009

This paper presents a high-speed Forward Error Correction (FEC) architecture based on three-parallel Reed-Solomon (RS) decoder for next-generation 100-Gb/s optical communication systems. A high-speed three-parallel RS(255,239) decoder has been designed and the derived structure can also be applied to implement the 100-Gb/s RS-FEC architecture. The proposed 100-Gb/s RS-FEC has been implemented with 0.13-${\mu}m$ CMOS standard cell technology in a supply voltage of 1.2V. The implementation results show that 16-Ch. RS-FEC architecture can operate at a clock frequency of 300MHz and has a throughput of 115-Gb/s for 0.13-${\mu}m$ CMOS technology. As a result, the proposed three-parallel RS-FEC architecture has a much higher data processing rate and low hardware complexity compared with the conventional two-parallel, three-parallel and serial RS-FEC architectures.