• Journal of Power Electronics
• /
• v.16 no.1
• /
• pp.121-132
• /
• 2016

In this paper, high-efficiency design methodology of a zero-voltage-switching full-bridge (ZVS-FB) pulse width modulation (PWM) converter for server-computer power supply is discussed based on self-driven synchronous rectifier (SR) performance. The design approach focuses on rectifier conduction loss on the secondary side because of high output current application. Various-number parallel-connected SRs are evaluated to reduce high conduction loss. For this approach, the reliability of gate control signals produced from a self-driver is analyzed in detail to determine whether the converter achieves high efficiency. A laboratory prototype that operates at 80 kHz and rated 1 kW/12 V is built for various-number parallel combination of SRs to verify the proposed theoretical analysis and evaluations. Measurement results show that the best efficiency of the converter is 95.16%.

• Journal of Power Electronics
• /
• v.12 no.3
• /
• pp.448-457
• /
• 2012

This paper proposes a carrier-based pulse width modulation (PWM) method to control an indirect matrix converter (IMC) by analyzing the relationship between the space vector PWM (SVPWM) and the carrier-based PWM. The complexity of the SVPWM method for an IMC can be reduced by using an equivalent carrier-based PWM method. The advantage of the proposed algorithm is its ability use only one symmetrical triangular carrier signal to generate the gate signals for all of the power switches in both the rectifier and inverter stages as compared to the conventional method where the carrier signal used in the rectifier stage is different from that of the inverter stage. In addition, by using a suitable offset voltage component in the modulation signals, the output voltage magnitude reaches 0.866 of the input voltage magnitude. Simulation and experimental results are provided in order to validate the proposed method.

• Journal of Power Electronics
• /
• v.12 no.1
• /
• pp.98-103
• /
• 2012

This paper presents a digital pulse width modulator (DPWM) with a reduced digital modulation delay (a transport delay of the modulator) during the transient response of power converters. During the transient response operation of a power converter, as a result of dynamic variations such as load step-up or step-down, the closed loop controller will continuously adjust the duty cycle in order to regulate the output voltage. The larger the modulation delays, the larger the undesired output voltage deviation from the reference point. The three conventional DPWM techniques exhibit significant leading-edge and/or trailing-edge modulation delays. The DPWM technique proposed in this paper, which results in modulation delay reductions, is discussed, experimentally tested and compared with conventional modulation techniques.

• Journal of Power Electronics
• /
• v.12 no.5
• /
• pp.708-714
• /
• 2012

This paper presents a new interleaved pulse-width modulation (PWM) boost-flyback converter to achieve power factor correction (PFC) and regulate DC bus voltage. The adopted boost-flyback converter has a high voltage conversion ratio to overcome the limit of conventional boost or buck-boost converter with narrow turn-off period. The proposed converter has wide turn-off period compared with a conventional boost converter. Thus, the higher output voltage can be achieved in the proposed converter. The interleaved PWM can further reduce the input and output ripple currents such that the sizes of inductor and capacitor are reduced. Since boundary conduction mode (BCM) is adopted to achieve power factor correction, power switches are turned on at zero current switching (ZCS) and switching losses are reduced. The circuit configuration, principle operation, system analysis, and design consideration of the proposed converter are presented in detail. Finally, experiments conducted on a laboratory prototype rated at 500W were presented to verify the effectiveness of the converter.

• Journal of Power Electronics
• /
• v.12 no.4
• /
• pp.643-653
• /
• 2012

An interleaved DC/DC converter with series-connected transformers is presented to implement the features of zero voltage switching (ZVS), load current sharing and ripple current reduction. The proposed converter includes two half-bridge converter cells connected in series to reduce the voltage stress of the switches at one-half of the input voltage. The output sides of the two converter cells with interleaved pulse-width modulation are connected in parallel to reduce the ripple current at the output capacitor and to achieve load current sharing. Therefore, the size of the output chokes and the capacitor can be reduced. The output capacitances of the MOSFETs and the resonant inductances are resonant at the transition instant to achieve ZVS turn-on. In addition, the switching losses on the power switches are reduced. Finally, experiments on a laboratory prototype (24V/40A) are provided to demonstrate the performance of the proposed converter.

• Journal of Power Electronics
• /
• v.12 no.2
• /
• pp.258-267
• /
• 2012

An interleaved single-stage AC/DC converter with a boost converter and an asymmetrical half-bridge topology is presented to achieve power factor correction, zero voltage switching (ZVS) and load voltage regulation. Asymmetric pulse-width modulation (PWM) is adopted to achieve ZVS turn-on for all of the switches and to increase circuit efficiency. Two ZVS half-bridge converters with interleaved PWM are connected in parallel to reduce the ripple current at input and output sides, to control the output voltage at a desired value and to achieve load current sharing. A center-tapped rectifier is adopted at the secondary side of the transformers to achieve full-wave rectification. The boost converter is operated in discontinuous conduction mode (DCM) to automatically draw a sinusoidal line current from an AC source with a high power factor and a low current distortion. Finally, a 240W converter with the proposed topology has been implemented to verify the performance and feasibility of the proposed converter.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.20 no.2
• /
• pp.130-136
• /
• 2015

This study describes the structure and operation modes of vertical stabilization (VS) converter for international thermonuclear experimental reactor (ITER) and proposes a protection method. ITER VS converter supplies voltage (${\pm}1000V$)/current (${\pm}22.5kA$) to superconducting magnets for plasma current vertical stabilization. A four-quadrant operation must be achieved without zero-current discontinuous section. The operation mode of the VS converter is separated in 12-pulse mode, 6-pulse mode and circulation current mode according to the magnitude of the load current. Protection measures, such as bypass and discharge, are proposed for abnormal conditions, such as over current, over voltage, short circuit, and voltage sag. VS converter output voltage is controlled to satisfy voltage response time within 20 msec. Bypass operation is completed within 60 msec and discharge operation is performed successfully. The feasibility of the proposed control algorithm and protection measure is verified by assembling a real controller and implementing a power system including the VS converter in RTDS for a hardware-in-loop (HIL) facility.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.42 no.12
• /
• pp.111-116
• /
• 2005

We propose a BASK (Binary Amplitude Shift Keying) system for Giga-bit Modem in millimeter band. The proposed system consists of a high speed shutter of the transmitter and a repeater of the receiver. The shutter of the proposed system is introduced for pulse shaping to improve the intersymbol interference (ISI). The repeater consists of several stage converters. A converter is constructed with a low pass filter and a limiter. The repeater can improve the signal-to-noise ratio (SNR) and make the rectangular pulse train. The proposed system is a simple system that uses conversion method without IF (Intermediate Frequency) process.

• Proceedings of the KIEE Conference
• /
• 1996.07a
• /
• pp.482-485
• /
• 1996

In this paper, a predictive current control of 12-pulse parallel connected dual converter system without interphase reactors(IPR) is presented. Firstly, the characteristics of system without IPR are analyzed and compared with that of system with IPR. And the predictive current control of this system is discussed. Finally the validity of the presented system and the excellence of the predictive current control response is proved through the simulation results.

• Journal of Power Electronics
• /
• v.12 no.5
• /
• pp.787-799
• /
• 2012

Real and reactive power flows on a transmission line interact inherently. This situation degrades power flow controller performance when independent real and reactive power flow regulation is required. In this study, a quasi multi-pulse interline power flow controller (IPFC), consisting of eight six-pulse voltage source converters (VSC) switched at the fundamental frequency is proposed to control real and reactive power flows dynamically on a transmission line in response to a sequence of set-point changes formed by unit-step reference values. It is shown that the proposed hybrid fuzzy-PI commanded IPFC shows better decoupling performance than the parameter optimized PI controllers with analytically calculated feed-forward gains for decoupling. Comparative simulation studies are carried out on a 4-machine 4-bus test power system through a number of case studies. While only the fuzzy inference of the proposed control scheme has been modeled in MATLAB, the power system, converter power circuit, control and calculation blocks have been simulated in PSCAD/EMTDC by interfacing these two packages on-line.