• Proceedings of the KIEE Conference
• /
• 2008.04a
• /
• pp.99-100
• /
• 2008

This paper proposes a Gaussian Mixture Model (GMM) - based speech emotion recognition methods using four feature parameters; 1) Fast Fourier Transform(FFT) spectral entropy, 2) delta FFT spectral entropy, 3) Mel-frequency Filter Bank (MFB) spectral entropy, and 4) delta MFB spectral entropy. In addition, we use four emotions in a speech database including anger, sadness, happiness, and neutrality. We perform speech emotion recognition experiments using each pre-defined emotion and gender. The experimental results show that the proposed emotion recognition using FFT spectral-based entropy and MFB spectral-based entropy performs better than existing emotion recognition based on GMM using energy, Zero Crossing Rate (ZCR), Linear Prediction Coefficient (LPC), and pitch parameters. In experimental Results, we attained a maximum recognition rate of 75.1% when we used MFB spectral entropy and delta MFB spectral entropy.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.1221-1224
• /
• 2003

A 64-point R2$^2$ SDF pipeline FFT processor using a new efficient computation sharing multiplier was designed. Computation sharing multiplication specifically targets computation re-use in multiplication of coefficient vector by scalar and is effectively used in DSP(Digital Signal Processing). To reduce the number of multipliers in FFT, we used the proposed computation sharing multiplier. The 64-point pipeline FFT processor was implemented by VHDL and synthesized using Max+PLUSII of Altera. The simulation result shows that the proposed computation sharing multiplier can be reduced to about 17.8% logic cells compared with a conventional multiplier. This processor can operate at 33MHz and calculate a 64-point pipeline FFT in 1.94 $mutextrm{s}$.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.11A
• /
• pp.1263-1270
• /
• 2004

A low-power 64-point FFT/IFFT processor core is designed, which is an essential block in OFDM-based wireless LAM modems. The radix-2/418 DIF (Decimation-ln-Frequency) FFT algorithm is implemented using R2SDF (Radix-2 Single-path Delay Feedback) structure. Some design techniques for low-power implementation are considered from algorithm level to circuit level. Based on the analysis on infernal data flow, some unnecessary switching activities have been eliminated to minimize power dissipation. In circuit level, constant multipliers and complex-number multiplier in data-path are designed using truncation structure to reduce gate counts and power dissipation. The 64-point FFT/IFFT core designed in Verilog-HDL has about 28,100 gates, and timing simulation results using gate-level netlist with extracted SDF data show that it can safely operate up to 50-MHz＠2.5-V, resulting that a 64-point FFT/IFFT can be computed every 1.3-${\mu}\textrm{s}$. The functionality of the core was fully verified by FPGA implementation using various test vectors. The average SQNR of over 50-dB is achieved, and the average power consumption is about 69.3-mW with 50-MHz＠2.5-V.

• Journal of Positioning, Navigation, and Timing
• /
• v.11 no.1
• /
• pp.11-21
• /
• 2022

Fast Fourier transform (FFT)-based parallel acquisition techniques with reduced computational complexity have been widely used for the acquisition of binary phase shift keying (BPSK) global positioning system (GPS) signals. In this paper, we propose a low computational FFT-based fine acquisition technique, for binary offset carrier (BOC) modulated BPSK signals, that depending on the subcarrier-to-code chip rate ratio (SCR) selectively utilizes the computationally efficient frequency-domain realization of the BPSK-like technique and two-dimensional compressed correlator (BOC-TDCC) technique in the first stage in order to achieve a fast coarse acquisition and accomplishes a fine acquisition in the second stage. It is analyzed and demonstrated that the proposed technique requires much smaller mean fine acquisition computation (MFAC) than the conventional FFT-based BOC acquisition techniques. The proposed technique is one of the first techniques that achieves a fast FFT-based fine acquisition of BOC signals with a slight loss of detection probability. Therefore, the proposed technique is beneficial for the receivers to make a quick position fix when there are plenty of strong (i.e., line-of-sight) GNSS satellites to be searched.

• Journal of the Korean Society of Radiology
• /
• v.12 no.4
• /
• pp.491-496
• /
• 2018

The purpose of this study is to analyze the noise spectra in DWI (diffusion-weighted imaging) pulse sequences of 1.5 Tesla and 3.0 Tesla MRI, The ACR (American College of Radiology) phantom and noise spectrum were analyzed by FFT (fast Fourier transform) and TFFT (temporal frequency analysis) using WavePad sound editor version 8.13 (NCH software, Greenwood Village, CO, USA). Noise spectra, FFT and TFFT were analyzed for laboratory 1.5Tesla and 3.0Tesla DWI MR pulse sequences. The noise threshold of the frequency amplitude in the FFT and TFFT at 3.0Tesla compared to 1.5Tesla was between 1.5Tesla and -6 dB, and between 3.0Tesla and 0 dB, the DWI pulse sequence for the patient's noise reduction was appropriately MR examination needs to be applied.

• 제어로봇시스템학회:학술대회논문집
• /
• 2002.10a
• /
• pp.94.1-94
• /
• 2002

This paper is concerned with parallel FFT and Quick-Merge Sort. They are implemented on computers interconnected by VMIC 5579 reflective memory and a cluster of workstations (PCs) interconnected via Fast Ethernet. Message passing interface (MPI) parallel library is used for communication in a cluster of workstations. An improved parallel FFT is also presented to decrease an execution time in the case of a small number of hosts. Distributed shared memory (DSM), VMIC 5579 reflective memory (RM), a cluster of workstations (COW) and message passing interface (MPI) parallel library are described.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.13 no.1
• /
• pp.35-41
• /
• 2020

Fast Fourier transform (FFT) processors have been widely used in various application such as communications, image, and biomedical signal processing. Especially, high-performance and low-power FFT processing is indispensable in OFDM-based communication systems. This paper presents a novel radix-26 FFT algorithm with low computational complexity and high hardware efficiency. Applying a 7-dimensional index mapping, the twiddle factor is decomposed and then radix-26 FFT algorithm is derived. The proposed algorithm has a simple twiddle factor sequence and a small number of complex multiplications, which can reduce the memory size for storing the twiddle factor. When the coefficient of twiddle factor is small, complex constant multipliers can be used efficiently instead of complex multipliers. Complex constant multipliers can be designed more efficiently using canonic signed digit (CSD) and common subexpression elimination (CSE) algorithm. An efficient complex constant multiplier design method for the twiddle factor multiplication used in the proposed radix-26 algorithm is proposed applying CSD and CSE algorithm. To evaluate performance of the previous and the proposed methods, 256-point single-path delay feedback (SDF) FFT is designed and synthesized into FPGA. The proposed algorithm uses about 10% less hardware than the previous algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.5
• /
• pp.32-38
• /
• 2009

FTT(Fast Fourier Transform) processor is widely used in OFDM(Orthogonal Frequency Division Multiplesing) system. Because of the increased requirement of mobility and bandwidth in the OFDM system, they need large point FTT processor. Since the size of memory which stores the twiddle factor coefficients are proportional to the N of FFT size, we propose a new method by which we can reduce the size of the coefficient memory. In the proposed method, we exploit a counter and unsigned multiplier to generate the twiddle factor indices. To verify the proposed algorithm, we design TFCGs(Twiddle Factor Coefficient Generator) for 1024pint FFTs with R2SDF(Radix-2 Single-Path Delay Feedback), $R2^3SDF,\;R2^3SDF,\;R2^4SDF$ architectures. The size of ROM is reduced to 1/8N. In the case of $R2^4SDF$ architecture, the area and the power are reduced by 57.9%, 57.5% respectively.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.7
• /
• pp.1370-1376
• /
• 2012

This paper proposes a gender recognition algorithm which classifies a male or female speaker. In this paper, characteristic vectors for the male and female speaker are analyzed, and recognition experiments for the proposed gender recognition by a neural network are performed using these characteristic vectors for the male and female. Input characteristic vectors of the proposed neural network are 10 LPC (Linear Predictive Coding) cepstrum coefficients, 12 LPC cepstrum coefficients, 12 FFT (Fast Fourier Transform) cepstrum coefficients and 1 RMS (Root Mean Square), and 12 LPC cepstrum coefficients and 8 FFT spectrum. The proposed neural network trained by 20-20-2 network are especially used in this experiment, using 12 LPC cepstrum coefficients and 8 FFT spectrum. From the experiment results, the average recognition rates obtained by the gender recognition algorithm is 99.8% for the male speaker and 96.5% for the female speaker.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.8B
• /
• pp.787-795
• /
• 2002

This paper presents the architecture and the implementation of a 2K/4K/8K-point complex Fast Fourier Transform(FFT) processor for Orthogonal Frequency-Division Multiplexing (OFDM) system. The architecture is based on the Cooley-Tukey algorithm for decomposing the long DFT into short length multi-dimensional DFTs. The transposition memory, shuffle memory, and memory mergence method are used for the efficient manipulation of data for multi-dimensional transforms. Booth algorithm and the COordinate Rotation DIgital Computer(CORDIC) processor are employed for the twiddle factor multiplications in each dimension. Also, for the CORDIC processor, a new twiddle factor generation method is proposed to obviate the ROM required for storing the twiddle factors. The overall 2K/4K/8K-FFT processor requires 600,000 gates, and it is implemented in 1.8 V, 0.18 ${\mu}m$ CMOS. The processor can perform 8K-point FFT in every 273 ${\mu}s$, 2K-point every 68.26 ${\mu}s$ at 30MHz, and the SNR is over 48dB, which are enough performances for the OFDM in DVB-T.