• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Research in Plant Disease
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• v.7 no.2
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• pp.112-115
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• 2001

Blossom blight of petunia caused by Choanephora cucurbitarum was found in greenhouses around Jinju area, Gyeongnam province, Korea in April 2001. The disease started with water-soaked lesions on the flower which rapidly withered and was rotten. Calyces developed water-soaked, dark-green lesions, and then were rotten. Whitish mycelia and monosporous sporangiola were produced on the lesions. The fungus isolated from the lesions produced white to pale yellowish brown mycelia with scattered monosporous sporangiola on potato-dextrose agar (PDA) plates. Size of sporangium was 37.2~135.8 um. Monosporous sporangiola were elliptic, fusiform or ovoid, and brown in color and their size was 10.4~22.4$\times$7.4~12.9 um. Sporangiospores were elliptic, fusiform or ovoid in shape, dark brown or brown in color and were 13.7~23.5$\times$8.7~13.8 um in size, and had appendaged appressorium of 3 or more. Zygospores were black, and 40.8~61.5 um in size. The fungus grew on PDA at 15-4$0^{\circ}C$, and optimum temperature was 3$0^{\circ}C$. This is the first report on the blossom blight of petunia caused by C. cucurbitarum in Korea.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.56-63
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• 2010

This work proposes a 12b 100MS/s 0.13um CMOS pipeline ADC for battery-powered mobile video applications such as DVB-Handheld (DVB-H), DVB-Terrestrial (DVB-T), Satellite DMB (SDMB), and Terrestrial DMB (TDMB) requiring high resolution, low power, and small size at high speed. The proposed ADC employs a three-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. A single shared and switched op-amp for two MDACs removes a memory effect and a switching time delay, resulting in a fast signal settling. A two-step reference selection scheme for the last-stage 6b FLASH ADC reduces power consumption and chip area by 50%. The prototype ADC in a 0.13um 1P7M CMOS technology demonstrates a measured DNL and INL within 0.40LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 60.0dB and a maximum SFDR of 72.4dB at 100MS/s, respectively. The ADC with an active die area of 0.92 $mm^2$ consumes 24mW at 1.0V and 100MS/s. The FOM, power/($f_s{\times}2^{ENOB}$), of 0.29pJ/conv. is the lowest of ever reported 12b 100MS/s ADCs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.4 s.119
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• pp.408-415
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• 2007

A switched-gain controlled LNA is designed and implemented in 0.18 um CMOS technology for $3.1{\sim}4.8\;GHz$ UWB system. In high gain mode, measurement shows a power gain of 12.5 dB, an input IP3 of 0 dBm, while consuming only 8.13 mA of current. In low gain mode, measurement shows a power gain of -8.7 dB, an input IP3 of 9.1 dBm, while consuming only 0 mA of current.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.2
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• pp.202-207
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• 2010

In this paper, a novel voltage-controlled oscillator(VCO) using the open loop multiple split ring resonator(OLMSRR) is presented for improving the phase noise, implemented in 130 nm CMOS technology. Compared with the conventional CMOS LC resonator, the proposed CMOS OLMSRR has the larger coupling coefficient value, which makes a higher Q-factor, and has improved the phase noise of the VCO. The proposed CMOS VCO based OLMSRR has the phase noise of -99.67 dBc/Hz @ 1 MHz in the oscillation frequency. Compared with the VCO using the conventional CMOS LC resonator and the proposed VCO using the CMOS OLMSRR structure has been improved in 7 dB. The prototype 24 GHz CMOS VCO is implemented in 130 nm CMOS and occupies a compact die area of $0.7\;mm{\times}0.9\;mm$.

• Proceedings of the Optical Society of Korea Conference
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• 1989.02a
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• pp.140-142
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• 1989

1.54um 파장에서 최대 형광을 나타내는 ZrF4-BaF2-LaF3-AlF3-NaF : ErF3 유리를 built-in-casting 법에 의해 제조하였다. Er+3 이온을 0.2몰부터 4몰까지 첨가하였으며, Er+3 이온의 4I13/2 준위의 lifetime 은 Er+3 이온 0.2몰부터 2몰까지 28msec로 최대값을 갖으며 4몰일때는 급격히 감소하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.129-131
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• 2011

An 6.4-Gb/s/channel 4-PAM transceiver is designed for a high speed memory application. The asymmetric 4-PAM signaling scheme is proposed to increase the voltage and time margins, and reduces the reference noise effect in a receiver by 33%. To reduce ISI in a channel, 1-tap pre-emphasis of a transmitter is used. The proposed asymmetric 4-PAM transceiver was implemented by using 0.13um 1-poly 6-metal CMOS process with 1.2V supply. The active area and power consumption of 1-charmel transceiver including a PLL are $0.294um^2$ and 6mW, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.98-107
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• 2013

This work describes a 13b 100 MS/s 0.13 um CMOS four-stage pipeline ADC for 3G communication systems. The proposed SHA-free ADC employs a range-scaling technique based on switched-capacitor circuits to properly handle a wide input range of $2V_{P-P}$ using a single on-chip reference of $1V_{P-P}$. The proposed range scaling makes the reference buffers keep a sufficient voltage headroom and doubles the offset tolerance of a latched comparator in the flash ADC1 with a doubled input range. A two-step reference selection technique in the back-end 5b flash ADC reduces both power dissipation and chip area by 50%. The prototype ADC in a 0.13 um CMOS demonstrates the measured differential and integral nonlinearities within 0.57 LSB and 0.99 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 64.6 dB and a maximum spurious-free dynamic range of 74.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.2 $mm^2$ consumes 145.6 mW including high-speed reference buffers and 91 mW excluding buffers at 100 MS/s and a 1.3 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.