• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.151-161
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• 2013

An active power factor correction (PFC) circuit is presented which employs a newly proposed input voltage sensor-less control technique operated in continuous conduction mode (CCM) and critical conduction mode (CRM). The conventional PFC circuit with input voltage sensor-less control technique degrades the power factor (PF) under the light load condition due to DCM operation. In the proposed PFC circuit, the switching frequency is basically 70KHz in CCM operation. In light load condition, however, the PFC circuit operates in CRM and the switching frequency is increased up to 200KHz. So CCM/CRM operation of the PFC circuit alleviates the decreasing of the PF in light load condition. The proposed PFC controller IC has been implemented in a $0.35{\mu}m$ BCDMOS process and a 240W PFC prototype is built. Experimental results shows the PF of the proposed PFC circuit is improved up to 10% from the one employing the conventional CCM/DCM dual mode control technique. Also, the PF is improved up to 4% in the light load condition of the IEC 61000-3-2 Class D specifications.

• Proceedings of the KIPE Conference
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• 2014.11a
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• pp.1-2
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• 2014

In this paper the partial switching PFC converter which is based on predictive control is proposed. In terms of satisfying the harmonic standard, the predictive control shows a similar performance to the conventional average current mode control PFC in the normal input condition. Moreover, the current harmonic characteristic is insensitive to the distorted input voltage. With predictive control method, novel on-line partial switching strategy is suggested in this paper. Depending on the operating condition, the partial switching PFC converter can boost its output voltage. Also when its efficiency needs to be improved, according to load condition, the partial switching can be achieved. The proposed strategy is proved by the results of FFT and the loss analysis using PSIM 9.0.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.84-91
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• 2009

A high speed serial link transmitter using multi-level signaling is proposed. To achieve high data rate m high speed serial link, 4-pulse amplitude modulation (PAM) is used. By transmitting 2 bit data in each symbol time, high speed data transmission, two times than binary signaling, is achieved. The transmitter transmits current-mode output instead of voltage-mode output Current-mode output is much faster than voltage-mode output, so higher data transmission is available by increasing switching speed of driver. $2^5-1$ pseudo-random bit sequence (PRBS) generator is contained to perform built-in self test (BIST). The 4-PAM transmitter is designed in Dongbu HiTek $0.18{\mu}m$ CMOS technology and achieves 8 Gb/s, 160 mV of eye height with 1.8 V supply voltage. The transmitter consumes only 98 mW for 8 Gb/s transmission.

• International journal of advanced smart convergence
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• v.8 no.4
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• pp.138-146
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• 2019

In this paper, we proposed a soft-switched synchronous buck converter, which can perform charging the battery. The proposed converter has low switching loss even at high frequency operation due to its soft switching characteristics. The converter operates in synchronous mode to minimize conduction loss, resulting in small conduction loss, also. In this reason, the efficiency of the converter can be greatly improved even in high frequency. The size and weight of the converter can be reduced by high frequency operation of the converter. In this paper, we designed a battery charger with a switching frequency of 100 kHz. The designed converter also simulated to prove the converter's characteristics of synchronous operation as well as soft switching operation. The simulation shows that the proposed converter always meets the soft switching conditions of turning on and off switching in the zero voltage and zero current states. Therefore, simulation results have confirmed that the proposed battery charger had soft switching characteristics. The simulation results for transient response to charge current for the designed converter show that the converter responds to charge current commands quickly within 0.05 ms.

• International Journal of Precision Engineering and Manufacturing
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• v.2 no.4
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• pp.81-88
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• 2001

We present a new digital phase measuring method for heterodyne optical interferometry, which providers high measuring speed up to 6 m/s with a fine displacement resolution of 0.1 nanometer. The key idea is combining two distinctive digital phase measuring techniques with mutually complementary characteristics to earth other one is counting the Doppler shift frequency counting with 20 MHz beat frequency for high-velocity measurement and the other is the synchronous phase demodulation with 2.0 kHz beat frequency for extremely fine displacement resolution. The two techniques are operated in switching mode in accordance wish the object speed in a synchronized way. Experimental results prove that the proposed dual mode phase measuring scheme is realized with a set of relatively simple electronic circuits of beat frequency shifting, heterodyne phase detection. and low-pass filtering.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.7
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• pp.711-719
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• 2008

Although non-real time simulation and pilot based evaluations are available for the development of flight control computer prior to real flight tests, there are still many risky factors. The control law designed for prototype aircraft often leads to degraded performance from the initial design objectives, therefore, the proper evaluation methods should be applied such that flight control law designed can be verified in real flight environment. The one proposed in this paper is IFS(In-Flight Simulator). Currently, this system has been implemented into the F-18 HARV(High Angle of Attack Research Vehicle), SU-27 and F-16 VISTA(Variable stability. In flight Simulation Test Aircraft) programs. This paper addresses the concept of switching mechanism for FLCC(Flight Control Computer)-SWMC(Switching Mechanism Computer) using 1553B communication based on flight control law of advanced supersonic trainer. And, the fader logic of TFS(Transient Free Switch) and stand-by mode of reset '0' type are designed to reduce abrupt transient and minimize the integrator effect in pitch axis control law. It hans been turned out from the pilot evaluation in real time that the aircraft is controllable during the inter-conversion process through the flight control computer, and level 1 handling qualities are guaranteed. In addition, flight safety is maintained with an acceptable transient response during aggressive maneuver performed in severe flight conditions.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1531-1534
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• 2009

Effect of process factors on the sensitivity of inner-type digital switching TSP was analyzed. From these results, we have successfully fabricated inner-type digital switching TSP embedded in 3.2-inch WQVGA PLS mode LCD panel. During many factors, TFT sensor structure for reducing the PI thickness and a separation distance of $0.3{\mu}m$ between the conductive column spacer (C/S) and TFT sensor were essential. Glass thickness and main C/S density were also important factors. This technology can be applied to wide angle of view hand-held phones, personal digital assistants (PDAs), and tablet PCs.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.875-878
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• 1998

In this thesis, we present efficient techniques to reduce the switching activity in a CMOS combinational logic network based on local logic transforms. But this techniques is not appropriate in the view of testability because of deteriorating the random pattern testability of a circuit. This thesis proposes a circuit design method having two operation modes. For the sake of power dissipation(normal operation mode), a gate output switches as rarely as possible, implying highly skewed signal probabilities for 1 or 0. On the other hand, at test mode, signals have probabilities of being 1 or 0 approaching 0.5, so it is possible to exact both stuck-at faults on the wire. Therefore, the goals of synthesis for low power and random pattern testability are achieved. The hardware overhead sof proposed design method are only one primary input for mode selection and AND/OR gate for each redundant connection.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.7
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• pp.589-594
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• 2009

We have studied electro-optic characteristics as a function of passivation thickness existing between common electrode and pixel electrodes in the fringe-field switching (FFS) mode using the LC with positive dielectric anisotropy. A steep increase in the transmission is observed with increase in the passivation layer from $0.29{\mu}m$ to $1.09{\mu}m$ and thereafter it almost saturates over the $1.09{\mu}m$ of passivation layer. This saturation is mainly associated with correlation between transmittance at the center region of pixel electrode and at the center region between pixel electrodes. From the results, optimal thickness of passivation layer can be defined.

• ETRI Journal
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• v.39 no.2
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• pp.292-299
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• 2017

We propose pulse-mode dynamic $R_on$ measurement as a method for analyzing the effect of stress on large-scale high-power AlGaN/GaN HFETs. The measurements were carried out under the soft-switching condition (zero-voltage switching) and aimed to minimize the self-heating problem that exists with the conventional hard-switching measurement. The dynamic $R_on$ of the fabricated AlGaN/GaN MIS-HFETs was measured under different stabilization time conditions. To do so, the drain-gate bias is set to zero after applying the off-state stress. As the stabilization time increased from $ 0.1{\mu}s$ to 100 ms, the dynamic $R_on$ decreased from $160\Omega$ to $2\Omega$. This method will be useful in developing high-performance GaN power FETs suitable for use in high-efficiency converter/inverter topology design.