• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.71-76
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• 2017

The electrical behavior and flexibility of the screen printed Ag circuits were investigated with infrared radiation sintering times and sintering temperatures. Electrical resistivity and radio frequency characteristics were evaluated by using the 4 point probe measurement and the network analyzer by using cascade's probe system, respectively. Electrical resistivity and radio frequency characteristics means that the direct current resistance and signal transmission properties of the printed Ag circuit. Flexibility of the screen printed Ag circuit was evaluated by measuring of electrical behavior during IPC sliding test. Failure mode of the Ag printed circuits was observed by using field emission scanning electron microscope and optical microscope. Electrical resistivity of the Ag circuits screen printed on Pl substrate was rapidly decreased with increasing sintering temperature and durations. The lowest electrical resistivity of Ag printed circuit was up to $3.8{\mu}{\Omega}{\cdot}cm$ at $250^{\circ}C$ for 45 min. The crack length arisen within the printed Ag circuit after $10{\times}10^4$ sliding numbers was 10 times longer than that of after $2.5{\times}10^4$ sliding numbers. Measured insertion loss and calculated insertion loss were in good agreements each other. Insertion loss of the printed Ag circuit was increased with increasing the number of sliding cycle.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.939-942
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• 2002

본문의 내용은 영구자석을 사용한 단상 브러시리스 모타의 구동을 위한 H-Brdige 구동회로에 적용된 전류제어 회로에 관한 실험결과이다. 부하전류가 목표치 이상인 경우 enable 를 차단하면 순간적으로 센서저항의 전위가 0 으로 되고 이로인해 다시 순간적으로 스위칭이 이루어 지므로 매우 빠른 주기로 스위칭을 반복한다. 이 문제점을 해결하기 위하여 래칭회로를 필요로 하는데, 본 제안에서는 두 개의 NAND GATE 와 하나의 NOT GATE, 그리고 RC network 를 조합하여 LIP-FLOP 과 시지연을 이루는 방법을 실현하였다. 이와 같은 전류제어회로는 constant off time 의 특성을 가지는데, 일반적으로 사용되는 PWM 제어회로에 비하여 매우 단순하면서도, 저항부하 및 모타부하에 대해 공히 능동적으로 작동함을 입증하고 있다. 본문에서는 제안된 전류제한회로의 구조와 H-bridge 구동모드, 그리고 전기적 특성에 대한 연구결과를 설명한다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.14 no.5
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• pp.29-34
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• 1977

Using JFET and bipolar transistor, we have designed a circuit of current controlled negative resitance and analysed this circuit in the operating region. Since the positive gate voltage of N-channel JFET is applied in full operating region, the output and transfer characteristics of JFET are measured in the positive gate region. The performances of this circuit are predicted from these characteristics and experimental results of the proposed CCNR circuit are presented.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.795-797
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• 2013

This paper describes a charge sharing capacitive-sensing circuit technique that improves the quality of images captured with fingerprint sensor LSIs. When the finger is dry, the electrical resistance of a finger surface is high. It leads to poor image quality. To capture clear images even when the finger is dry, the modified capacitive detection circuit improves the image quality using an enhancement plate at the finger surface and a voltage control circuit. The test circuit is analyzed on $0.35{\mu}m$ CMOS process.

• Journal of the Korean Institute of Telematics and Electronics
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• v.8 no.2
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• pp.24-33
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• 1971

A noble method of delta modulation by means of pair transistor circuit having negative resistance charcteristic is presented. An RC parallel circuit is inserted between two eiuitter tarminals of the pair transistor circuit, and their emitters are driven by a square pulsed current source. Basically this is a relaxation oscillator circuit. But when the value of capacitors and resistanc R, and the pulse height of driving source are properly chosen, the RC parallel circuit apparently functions as integrating circuit of driviving pulses. Compared with the integrated voltage of capacitor C, a signal input voltatage supplied in series with RC parallel circuit between two emitters makes on or off either of the pair transistors. as the result, one bit pulse is sent out from the coupling resistance terminal of conducted transistor. The circuit diagram used for this experiment is presented, it i% composed with simple mod ulster circuit, differential amplifier and pulse shaping amplifier, The characteristics of the components of this ciruit are discussed, and especially quantumized noise in this delta modulation system is discussed in order to improve the signal to noise ratio which has a close relation with circut constants, quantumized voltage, pulse height and width of driving current source.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.359-362
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• 1998

2차원 혼합 모드 소자-회로 시뮬레이터를 이용한 과도상태 해석의 알고리즘을 제시한다. 1변수 muller 및 regular falsi법을 회로의 절점 전압과 분기(branch) 전류를 계산하는데 적용하였다. 제안된 알고리즘의 정확도와 유호성을 검증하기 위해 PN 다이오드의 양극(anode)에 저항이 직렬로 연결된 회로의 모의실험을 수행한 결과, MEDICI의 모의실험 결과에 비해 과도상태에서 전류 및 전압 특성은 각각 0.06%, 0.2% 오차 범위 한도 내에서 일치함을 보였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.1
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• pp.241-250
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• 2000

Chua's circuit is a simple electronic network which exhibits a variety of bifurcation and attractors. The circuit consists of two capacitors, an inductor, a linear resistor, and a nonlinear resistor. In this paper, a transmitter and a receiver using two identical Chua's circuits are proposed and synchronizations and secure communication of a lossy equivalent transmission are investigated. Since the synchronization of the lossy equivalent transmission system is impossible by coupled synchronization, theory having both the drive-response and the coupled synchronization is proposed. The proposed method is synthesizing the desired information with the chaos circuit by adding the information signal to the chaos signal in the lossy equivalent transmission system.

• Journal of the Korean Institute of Telematics and Electronics
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• v.12 no.5
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• pp.1-5
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• 1975

접합형 트린지스터와 발광다이오드(LED) 및 광도전소자(CdS)로서 구성된 광결합 전류안정부저항회로를 진안하였다. 이는 일반적으로 광트랜지스터보다도 더 예민한 것을 이용하여, CdS와 LED를 밀착 시켜서 LED에 흐르는 전류와 CdS의 실효저항변화로써 결합된 광결합방식을 택하였다. 트랜지스터의 콜랙터-에미터간에 인위적인 누변저항을 삽입하는 방법을 도입함으로써 부저항치 및 최대입력단자전압치를 임의로 변화할 수 있게 하였으며, 제안한 회로를 분석하고 또 이를 실험적으로 확인하였다. 누변저항을 1KΩ에서 30KΩ까지 변화시켰을 때 최대입력단자전압은 1.65V에서 4.22V로 변하였고, 부저항치는 -1.0KΩ에서 -10.0KΩ까지 변하였다. 또 실험치에 대한 계산치에의 상대백분최대오차가 11%이었다. A current stable negative resistance circuit has been constucted with combination of coulplementary symmetrical transistors, a light emitting diode and a photoconductive cell. The negative resistance(Rn) and break-over voltage(VBo) can be set at a designed value according to adjustment of the artificial leakage resistance of p-n-p transistor. The RN and VBo calculated in this designed circuit are checked though the experiments, the errors are found less than 11%.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.2
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• pp.22-27
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• 1978

An improved active R filter is proposed which contains only resistors and two operational amplifiers represented by their single pole model. The filter has very low sensitivities to all circuit parameters, is suitable for low frequency and low 9 applications in addition to high frequency and high 0, and realizes various biquadratic transfer functions simultaneously with lower resistance ratios. The independent control of design specifications is possible in the circuit. Experimental results in laboratory are presented.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.579-580
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• 2008

DRAM설계시 DDR2에서부터 고속 동작으로 인해 반송파에 의한 신호외곡으로 impedance matching의 필요성이 대두되었다. 이로 인해 제안된 방법은 외부 Termination 저항(RZQ)을 기준으로 impedance matching을 위한 Rtt 저항의 생성이다.[1] 제안된 ZQ Calibration 회로는 기존의conventional ZQ Calibration 회로에 After ZQ calibration block을 추가하여 한 번 더 교정함으로써 마지막 PMOS Array와 NMOS Array 저항 값이 Termination 저항 값에 가깝도록 설계하였다. 따라 전력효율은 그대로 유지하면서 ${\Delta}VM$의 오차범위를 기존의 ${\pm}5%$이내에서 skew 조건에 따라 ${\pm}1.33%$까지 향상시키는 것을 볼 수 있다. (JEDEC spec. ${\pm}5%$이내).