• Title/Summary/Keyword: 회로구조

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Analysis of Quality factor and Effective inductance of Inductor for RF Integrated Circuits in 90nm CMOS Technology (RFIC 설계에 응용 가능한 90nm 공정 기반 인덕터의 Quality factor 및 Effective inductance 분석)

  • Jang, Seong-Yong;Shin, Jong-Kwan;Kwon, Hyuk-Min;Kwon, Sung-Kyu;Sung, Seung-Yong;Hwang, Sun-Man;Jang, Jae-Hyung;Lee, Ga-Won;Lee, Hi-Deok
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.5
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    • pp.128-133
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    • 2013
  • In this paper, octagonal inductors for RFIC designs was fabricated with 90nm CMOS Technology to compare its quality factor and the effective inductance as functions of radius and number of turn. The quality factor decreases as the inner radius and the number of metal turned increase. However, the effective inductance increases with the increasing the inner radius and the number of metal turned. Therefore, the inductor structure should be decided according to the relative importance of Q-factor and inductance.

Design of MMIC Low Noise Amplifier for B-WLL using GaAs PHEMT (GaAs PHEMT를 이용한 B-WLL용 MMIC 저잡음 증폭기의 설계)

  • 김성찬;이응호;조희철;조승기;김용호;이진구
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.11 no.1
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    • pp.102-109
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    • 2000
  • In this paper, a Low Noise Amplifier for B-WLL was designed using the MMIC technology with GaAs PHEMTs fabricated at our lab. The PHEMT for LNA has a $0.35\mu\textrm{m}$ gate and a total gate width of $120\mu\textrm{m}$. The designed MMIC LNA consists of three stages. The first stage of the LNA has a series inductive feedback for obtaining minimum noise and high stability as well. And the designed MMIC LNA has not an interstage matching circuit between the second and the third stage for minimization of the chip size. From simulation results, noise figure and S21 gain of the designed MMIC LNA are 0.85~1.25 dB and 22.08~23.65 dB in the frequency range of 25.5~27.5 GHz respectively. And the chip size is $3.7\times1.6 mm^2$.

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Antenna Efficiency Measurement Using the Modified Wheeler Cap Method (개선된 Wheeler Cap 방식을 이용한 안테나 효율 측정)

  • Cho Chi-Hyun;Choo Ho-Sung;Park Ik-Mo;Kang Jin-Seob
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.17 no.4 s.107
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    • pp.317-323
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    • 2006
  • The conventional Wheeler cap method can extract the reliable efficiency of the antenna when the antenna operates as a simple series or parallel RLC circuit model. This method, however, may give an unreliable efficiency when the antenna under test has a complicated operating principle. In this paper, we revisit the conventional Wheeler cap method and propose a modified Wheeler cap method basedon the high-order circuit model. The proposed method can provide an accurate efficiency even for the antenna with a more complicated operating principle. Then we calculate efficiencies of other antennas with different operating principles and compare the results with the simulations.

Design of Embedded Electrical Power Control Unit for Personal Electrical Vehicle (1인승 전기차량의 임베디드 전동제어장치 설계)

  • Shin, Kyoo-Jae;Cha, Hyun-Rok
    • Journal of IKEEE
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    • v.18 no.2
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    • pp.282-290
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    • 2014
  • This paper presents the design of embedded electrical power control unit for Personal Electrical Vehicle(PEV). The embedded unit is designed using PIC18F8720 processor, 16Mb flash ROM, 32Mb SDRAM and signal condition circuits. The proposed PEV consists of 4KW in-wheel Brushless DC Motor(BLDCM), 3 phase voltage source inverter with the $180^{\circ}$ conduction space vector PWM method, PID speed controller and the embedded control unit. The PEV has mechanical manufacture of inverse 3 wheel system, which is applied by the in-wheel BLDCM and steering mechanism with tilting function. Also, the performances of the proposed embedded electrical power control unit are verified through the lab experiment and road driving test of PEV.

Development of an Artificial Neural Network Expert System for Preliminary Design of Tunnel in Rock Masses (암반터널 예비설계를 위한 인공신경회로망 전문가 시스템의 개발)

  • 이철욱;문현구
    • Geotechnical Engineering
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    • v.10 no.3
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    • pp.79-96
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    • 1994
  • A tunnel design expert system entitled NESTED is developed using the artificial neural network. The expert system includes three neural network computer models designed for the stability assessment of underground openings and the estimation of correlation between the RMR and Q systems. The expert system consists of the three models and the computerized rock mass classification programs that could be driven under the same user interface. As the structure of the neural network, a multi -layer neural network which adopts an or ror back-propagation learning algorithm is used. To set up its knowledge base from the prior case histories, an engineering database which can control the incomplete and erroneous information by learning process is developed. A series of experiments comparing the results of the neural network with the actual field observations have demonstrated the inferring capabilities of the neural network to identify the possible failure modes and the support timing. The neural network expert system thus complements the incomplete geological data and provides suitable support recommendations for preliminary design of tunnels in rock masses.

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Compact Range Detection Sensor by Oscillation Frequency Deviation of an Active Antenna (능동안테나의 발진주파수 편이에 의한 소형 거리 센서)

  • Yun, Gi-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.3
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    • pp.528-535
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    • 2011
  • In this paper, a compact doppler sensor with oscillator type active antenna operating at 2.4GHz frequency band is proposed to measure the distance to a moving object. The oscillation frequency is shifted depending on approaching of the object, and a detection circuit discriminates the frequency deviation. The active antenna has been designed and simulated. The prototype fabricated has a small circular disk type of diameter 30mm and height 4.2mm. As for antenna performance, broadside radiation pattern with beamwidth of $120^{\circ}$ and oscillation frequency of 2.35GHz has been measured. Test results as a range sensor shows that signal voltage of about 240mV has been obtained for conducting plate moving 1 meter away from the sensor. And, signal voltage has been linearly increased to the ground from 5m height by free-falling the sensor.

GPGPU Acceleration of SAT Algorithm with Propagation Routine Parallelization (전달 루틴의 병렬화를 통한 SAT 알고리즘의 GPGPU 가속화)

  • Kang, Hyeong-Ju
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.10
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    • pp.1919-1926
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    • 2016
  • Because of the enormous processing ability, General-Purpose Graphics Processing Unit(GPGPU) has been applied to many fields including electronics design automation. The SAT algorithm is one of the core algorithm in many electronics design automation tools. There has been some efforts to apply GPGPU to the SAT algorithm, but it is difficult to parallelize the SAT algorithm because of its characteristics. In this paper, I applied GPGPU to the SAT algorithm by parallelizing the propagation routine that is relatively suitable to parallel processing. On the basis of the similarity of the propagation routine to the sparse matrix multiplication, the data structure for the SAT problem is constituted, and the parallel propagation routine is described. To prevent data loss between paralllel threads, atomic operations are exploited. The experimental results for some benchmark SAT problems show that the proposed algorithm is superior to the previous GPGPU-based SAT solver.

A New High Efficiency Phase Shifted Full Bridge Converter for Sustaining Power Module of Plasma Display Panel (PDP 유지전원단을 위한 높은 효율을 갖는 새로운 페이지쉬프트 풀브릿지 컨버터)

  • Lee, Woo-Jin;Kim, Chong-Eun;Han, Sang-Kyoo;Moon, Gun-Woo
    • Proceedings of the KIPE Conference
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    • 2005.07a
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    • pp.445-448
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    • 2005
  • A new high efficiency phase shifted full bridge (PSFB) converter for sustaining power module of plasma display panel (PDP) is proposed in this paper .The proposed converter employs the rectifier of voltage doubler type without output inductor. Since it has no output inductor, the voltage stresses of the secondary rectifier diodes can be clamped at the level of the output voltage. Therefore, no dissipative resistor-capacitor (RC) snubber for rectifier diodes is needed and a high efficiency as well as low noise cutout voltage can be realized. In addition, due to elimination of the large output inductor, it features a simple structure, lower cost, less mass, and lighter weight. Furthermore, the proposed converter has wide zero voltage switching (ZVS ) ranges with low current stresses of the primary switches. Also the resonance between the leakage inductor of the transformer and the capacitor of the voltage doubler cell makes the current stresses of the primary switches and rectifier diodes reduced. In this paper, the operational principles, analysis of the proposed converter, and the experimental results are presented.

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Logic Synthesis Algorithm for TLU-Type FPGA (TLU형 FPGA를 위한 기술 매핑 알고리즘)

  • Park, Jang-Hyeon;Kim, Bo-Gwan
    • The Transactions of the Korea Information Processing Society
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    • v.2 no.5
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    • pp.777-786
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    • 1995
  • This paper describes several algorithms for technology mapping of logic functions into interesting and popular FPGAs that use look-up table memories. In order to improve the technology mapping for FPGA, some existing multi-level logic synthesis, decomposition reduction and packing techniques are analyzed and compared. And then new algorithms such as node-pair decomposition, merging fanin, unified reduction and multiple output decomposition which are used for combinational logic design, are proposed. The cost function is used to minimize the number of CLBs and edges of the network. The cost is a linear combination of each weight that is given by user. Finally we compare our new algorithm with previous logic design technique[8]. In an experimental comparison our algorithm requires 10% fewer CLB and nets than SIS-pga.

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Improvement of DS System using Transversal Filter for Advanced Duty Rate on Meteor Burst Channel (유성 버스트 채널 도통율 향상을 위해 Transversal Filter를 적용한 DS시스템의 개선)

  • Kwon Hyeog-Soong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.6A
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    • pp.627-633
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    • 2006
  • In spite of many advantages of Meteor Burst Communications(MBC) on its transmission channel, the fact that its duty rate is less than 10 percents is a considerable deficiency of MBC. To overcome with this deficiency without paying large cost, we use a direct sequence(DS) simple reception system. This method doesn't need to add the components for acquisition or tracking the signal so that it keeps the cost efficiency of the MBC. But it has a disadvantage that its duty rate shows a large decline by noise. For this problem we adopt the proposed system applying a transversal filter circuit. The improvement by this method is more significant when the received signal is weak Simulation results show as t1 is 100ms, then the burst length would be increased by 35% when the initial value of the received signal power increases by 3 dB, t2 is 135ms. If the power increases by 6dB the burst length would be 170ms thus increased by 70%, which shows a great enhancement. Suppose now that t1 is 50ms and the power is increased by 3dB, then t2 would be increased by 70% to 85ms, and increasing the power by 6dB it would be increased by 130% to 115ms.