• Journal of IKEEE
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• v.19 no.3
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• pp.378-384
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• 2015

In conventional HEVC inverse core transform architectures, extra $n{\times}n$ inverse transform block is added to $2n{\times}2n$ inverse transform block, and it operates as one $2n{\times}2n$ inverse transform block or two $n{\times}n$ inverse transform blocks. Thus, same number of pixels are processed in the same time, but it suffers from increased hardware size due to extra $n{\times}n$ inverse transform block. To avoid this problem, a novel $8{\times}8$ HEVC inverse core transform architecture was proposed to eliminate extra $4{\times}4$ inverse transform block based on multiplier reuse. This paper extends this approach and proposes a novel HEVC $16{\times}16$ inverse core transform architecture. Its frame processing time is same in $4{\times}4$, $8{\times}8$, and $16{\times}16$ inverse core transforms, and reduces gate counts by 13%.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.12
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• pp.41-50
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• 1999

In this paper, the new VLSI architecture of a reconstruction filter for morphological image segmentation is proposed. The filter, based on the $h_{max}$ operation, simplifies the interior of each region while preserving the boundary information. The proposed architecture adopts a partitioned memory structure and an efficient image scanning strategy to reduce the operations. The proposed memory partitioning scheme makes it possible that every data required for processing can be read from each memory at a time, resulting in parallel data processing. By the extended connectivity consideration, the operation is much decreased because more simplification is achieved in scanning stage. The selective raster scan strategy endows the satisfactory noise removal capability with negligible hardware complexity increase. The proposed architecture is designed using VHDL, and functional evaluation is performed by the CAD tool, Mentor. The experiment results show that the proposed architecture can simplify image profile with less than 18% operations of the conventional method.

• Journal of IKEEE
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• v.19 no.1
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• pp.1-9
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• 2015

This paper proposes the design of sub-pixel interpolation circuit for real-time multi-decoder supporting 4K-UHD video images. The proposed sub-pixel interpolation circuit supports H.264, MPEG-4, VC-1 and new video compression standard HEVC. The common part of the interpolation algorithm used in each video compression standard is shared to reduce the circuit size. An intermediate buffer is effectively used to reduce the circuit size and optimize the performance. The proposed sub-pixel interpolation circuit was synthesised by using 130nm standard cell library. The synthesized gate-level circuit consists of 122,564 gates and processes 35~86 image frames per second for 4K-UHD video at the maximum operation frequency of 200MHz. Therefore, the proposed circuit can process 4K-UHD video in real time.

• Journal of Sensor Science and Technology
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• v.10 no.6
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• pp.317-327
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• 2001

In this paper, we proposed a new detection method of pH image to effectively measure a 2-dimensional pH distribution of test materials by irradiating an frequency modulated light to LAPS using a reticle. It could measure simultaneously signals in one line by applying a modulated light having difference frequency for each pixel using a frequency modulating reticle, and calculating an amplitude with respect to a frequency component by the light source. To experiment the proposed method, we designed and implemented a reticle considering of a LAPS's characteristic, and reconstructed an image by frequency analysis using the implemented reticle and test pattern image. As a result, we verified that the proposed method using the reticle was able to detect 30 times faster for a $30{\times}30$ pixels pH image having a PSNR of 22-24 [dB] than conventional method.

• Journal of the Korea Society of Computer and Information
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• v.13 no.3
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• pp.179-187
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• 2008

In this paper, we apply a set of algorithms to classily normal and cancer nucleus from uterine cervical pap-smear images. First, we use lightening compensation algorithm to restore color images that have defamation through the process of obtaining $1{\times}400$ microscope magnification. Then, we remove the background from images with the histogram distributions of RGB regions. We extract nucleus areas from candidates by applying histogram brightness, Kapur method, and our own 8-direction contour tracing algorithm. Various binarization, cumulative entropy, masking algorithms are used in that process. Then, we are able to recognize normal and cancer nucleus from those areas by using three morphological features - directional information, the size of nucleus, and area ratio - with fuzzy membership functions and deciding rules we devised. The experimental result shows our method has low false recognition rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.335-344
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• 2003

The image compression based on discrete wavelet transform has been widely accepted in industry since it shows no block artifacts and provides a better image quality when compressed to low bits per pixel, compared to the traditional JPEG. The coefficients generated by discrete wavelet transform are quantized to reduce the number of code bits to represent them. After quantization, lossless coding processes are usually applied to make further reduction. This paper presents a new and efficient lossless coding algorithm for quantified wavelet coefficients based on the statistical properties of the coefficients. Combined with discrete wavelet transform and quantization processes, our algorithm has been implemented as an image compression chip, using 0.5${\mu}{\textrm}{m}$ standard cells. The experimental results show the efficiency and performance of the resulting chip.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.28-34
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• 2011

In this paper, we present integer and fractional motion estimation IP for H.264/AVC encoder by hardware-oriented algorithm. In integer motion engine, the reference block is used to share for consecutive current macro blocks in parallel processing which exploits data reusability and reduces off-chip bandwidth. In fractional motion engine, instead of two-step sequential refinement, half and quarter pel are processed in parallel manner in order to discard unnecessary candidate positions and double throughput. The H.264/AVC motion estimation chip is fabricated on a MPW(Multi-Project Wafer) chip using the chartered $0.18{\mu}m$ standard CMOS 1P5M technology and achieves high throughput supporting HDTV 720p 30 fps.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.6
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• pp.133-141
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• 2008

As interactive multimedia have come into wide use, user interfaces such as remote controllers or classical computer mice have several limitations that cause inconvenience. We propose a vision-based pointing device to resolve this problem. We analyzed the moving image from the camera which is embedded in the pointing device and estimate the movement of the device. The pose of the cursor can be determined from this result. To process in the real time, we used the low resolution of $288{\times}208$ pixel camera and comer points of the screen were tracked using local optical flow method. The distance from screen and device was calculated from the size of screen in the image. The proposed device has simple configurations, low cost, easy use, and intuitive handhold operation like traditional mice. Moreover it shows reliable performance even in the dark condition.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.2
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• pp.165-171
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• 2004

Owing to small sizes and high density to the semiconductor It, it is difficult to discriminate the defects of ICs by human eyes. High precision inspection system with computer vision is essentially established for the manufacturing process due to the variety of defective parts. Especially it is difficult to implement the algorithm for the coplanarity of IC leads. Therefore in this paper, the inspection system which can detect the defects of the SOP types of ICs having 1cm${\times}$0.5cm of the chip size is implemented and evaluated it's performance. In order to optimally detect various items, some principles of geometry are theoretically presented , length measurement, pitch measurement, angle measurement, brightness of image and correcton of position. The interface circuit is designed for implementation of inspection system and connected the HANDLER. In the result, the system could detect two ICs' defects per second and confirmed the resolution of 20$\mu$m per pixel.

• Korean Journal of Optics and Photonics
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• v.33 no.6
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• pp.303-309
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• 2022

Since the pixel size of the image sensor used in optical systems is gradually decreasing, the resolution specification of the optical system should be inevitably higher. If aberration change according to the eccentricity of a specific lens group occurs, only the amount of eccentricity of a specific lens group may be calculated with the traditional resolution adjustment method so that the aberration of the optical system is minimized to a certain extent. As a result, it is possible to increase the resolution of the optical system and to respond to a sensor with a large number of pixels. However, in the traditional method, there should be no change in specific aberration due to the eccentricity of a specific lens group. In this paper, we propose a new method to eliminate such a limitation of the traditional method in a camera optical system with a floating system, which is to choose and control the arbitrary two lens groups to easily minimize the eccentricity of the optical system in order to obtain an optical system with high resolution.