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Electrical Resistivity Surveys in Yangsan Fault Area near Kyongju (경주 부근 양산단층 지역에서의 전기비저항 탐사)

  • Lee, Gi Hwa;Han, Won Seok
    • Journal of the Korean Geophysical Society
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    • v.2 no.4
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    • pp.259-268
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    • 1999
  • Electrical resistivity surveys were conducted in the areas between Buji-ri and Seoak-dong, and between Nawon-ri and Yangdong-ri, Kyongju in order to investigate the geoelectric structure of the nothren part of the Yangsan Fault. In the area between Buji-ri and Seoak-dong south of Kyongju, the fracture zone east of the inferred fault develops more deeply, without significant north-south variation in depth, than west. In the area between Nawon-ri and Yangdong-ri north of Kyongju, the fault zone seems to be developed along the Hyungsan-river, and the resistivity structure west of the river is more affected by the fracture zone than east. Interpreted section of dipole-dipole survey conducted in Homyung-ri shows vertical contact of the Yangsan Fault. It appears that the boundary between the northern and central segment of the Yangsan Fault is located in the north of study areas since there is no significant variation in electrical resistivity structure near Kyongju.

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Gradient Magnitude Hardware Architecture based on Hardware Folding Design Method for Low Power Image Feature Extraction Hardware Design (저전력 영상 특징 추출 하드웨어 설계를 위한 하드웨어 폴딩 기법 기반 그라디언트 매그니튜드 연산기 구조)

  • Kim, WooSuk;Lee, Juseong;An, Ho-Myoung
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.10 no.2
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    • pp.141-146
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    • 2017
  • In this paper, a gradient magnitude hardware architecture based on hardware folding design method is proposed for low power image feature extraction. For the hardware complexity reduction, the projection vector chracteristic of gradient magnitude is applied. The proposed hardware architecture can be implemented with the small degradation of the gradient magnitude data quality. The FPGA implementation result shows the 41% of logic elements and 62% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v16.0 environment.

Image Filter Optimization Method based on common sub-expression elimination for Low Power Image Feature Extraction Hardware Design (저전력 영상 특징 추출 하드웨어 설계를 위한 공통 부분식 제거 기법 기반 이미지 필터 하드웨어 최적화)

  • Kim, WooSuk;Lee, Juseong;An, Ho-Myoung;Kim, Byungcheul
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.10 no.2
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    • pp.192-197
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    • 2017
  • In this paper, image filter optimization method based on common sub-expression elimination is proposed for low-power image feature extraction hardware design. Low power and high performance object recognition hardware is essential for industrial robot which is used for factory automation. However, low area Gaussian gradient filter hardware design is required for object recognition hardware. For the hardware complexity reduction, we adopt the symmetric characteristic of the filter coefficients using the transposed form FIR filter hardware architecture. The proposed hardware architecture can be implemented without degradation of the edge detection data quality since the proposed hardware is implemented with original Gaussian gradient filtering algorithm. The expremental result shows the 50% of multiplier savings compared with previous work.

A study on the highly sensitive metal nanowire sensor for detecting hydrogen (수소감지를 위한 고감도의 금속 나노선 센서에 관한 연구)

  • An, Ho-Myoung;Seo, Young-Ho;Yang, Won-Jae;Kim, Byungcheul
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.9
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    • pp.2197-2202
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    • 2014
  • In this paper, we report on an investigation of highly sensitive sensing performance of a hydrogen sensor composed of palladium (Pd) nanowires. The Pd nanowires have been grown by electrodeposition into nanochannels and liberated from the anodic aluminum oxide (AAO) template by dissolving in an aqueous solution of NaOH. A combination of photo-lithography, electron beam lithography and a lift-off process has been utilized to fabricate the sensor using the Pd nanowire. The hydrogen concentrations for 2% and 0.1% were obtained from the sensitivities (${\Delta}R/R$) for 1.92% and 0.18%, respectively. The resistance of the Pd nanowires depends on absorption and desorption of hydrogen. Therefore, we expect that the Pd nanowires can be applicable for detecting highly sensitive hydrogen gas at room temperature.

Physical correlation between annealing process and crystal structure and magneto-resistance of Bismuth thin films (열처리 공정과 비스무스 박막의 결정구조 및 자기저항 특성변화와의 물리적 관계)

  • Jang, Seok Woo;Seo, Young-Ho;An, Ho-Myoung
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.3
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    • pp.638-642
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    • 2014
  • In this study, we investigate on the crystal microstructure and magneto-resistance (MR) change of Bismuth(Bi) thin films for annealing process, in order to apply Bi thin films to the spin electronic devices. As-prepared Bi thin films show the randomly oriented find grains whose size was measured to about 100 nm and the very low MR (4.7 % at room temperature) while careful annealing results in not only grain growth up to ${\sim}2{\mu}m$ but also drastic MR improvement (404 % at room temperature). The drastic change in the MR after applying the annealing process is attributed to the grain growth decreasing grain boundary scattering of electron. Therefore, in this study, we confirm the annealing effect for the grain boundary formation and MR improvement of Bi thin films, and demonstrate the feasibility of spin electronic devices.

Design of the 140W level-small sized LED Power Control Circuit (140W 급-저면적 LED 전원 제어 회로 설계)

  • An, Ho-Myoung;Lee, Juseong;Kim, Byungcheul
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.11 no.5
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    • pp.586-592
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    • 2018
  • In this paper, HIC with various functions is proposed for the design 140W LED power control circuit. The proposed HIC integrates constant voltage/constant current circuit, short circuit protection circuit, internal constant voltage circuit, and dimmer circuit, thereby reducing the horizontal length of the PCB by 16% comparing with the conventional system. Through various experiments, we verified the performance of each block implemented inside of HIC with numerical results. (Constant voltage variation ratio: 2.9%, dimmer circuit duty variation within 5%, stable short protection at 720 mA) Since the PCB area can be significantly reduced by applying the proposed HIC. It is possible to reduce the PCB manufacturing time which takes up most of the manufacturing time, however, It is expected that the faulted power module can be replaced without replacing the whole PCB, so that maintenance / repair can be made easier.

A Study on Implementation of the High Speed Feature Extraction System Based on Block Type Classification (블록 유형 분류 알고리즘 기반 고속 특징추출 시스템 구현에 관한 연구)

  • Lee, Juseong;An, Ho-Myoung
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.12 no.3
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    • pp.186-191
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    • 2019
  • In this paper, we propose a implementation approach of the high-speed feature extraction algorithm. The proposed method is based on the block type classification algorithm which reduces the computation time when target macro block is divided to smooth block type that has no image features. It is quantitatively identified that occurs at 29.5% of the total image using 200 standard test images with $64{\times}64$ macro block size. This means that within a standard test image containing various image information, 29.5% can reduce the complexity of the operation. When the proposed approach is applied to the Canny edge detection, the required latency of the edge detection can be completely eliminated, such as 2D derivative filter, gradient magnitude/direction computation, non-maximal suppression, adaptive threshold calculation, hysteresis thresholding. Also, it is expected that operation time of the feature detection can be reduced by applying block type classification algorithm to various feature extraction algorithms in this way.

Improvement of Power Consumption of Canny Edge Detection Using Reduction in Number of Calculations at Square Root (제곱근 연산 횟수 감소를 이용한 Canny Edge 검출에서의 전력 소모개선)

  • Hong, Seokhee;Lee, Juseong;An, Ho-Myoung;Koo, Jihun;Kim, Byuncheul
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.13 no.6
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    • pp.568-574
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    • 2020
  • In this paper, we propose a method to reduce the square root computation having high computation complexity in Canny edge detection algorithm using image processing. The proposed method is to reduce the number of operation calculating gradient magnitude using pixel's continuity using make a specific pattern instead of square root computation in gradient magnitude calculating operation. Using various test images and changing number of hole pixels, we can check for calculate match rate about 97% for one hole, and 94%, 90%, 88% when the number of hole is increased and measure decreasing computation time about 0.2ms for one hole, and 0.398ms, 0.6ms, 0.8ms when the number of hole is increased. Through this method, we expect to implement low power embedded vision system through high accuracy and a reduced operation number using two-hole pixels.

Prevalence of antibodies to Coxiella burnetii in ruminants in Gwangju area, South Korea (광주지역 반추동물의 큐열 항체 보유율 조사)

  • Oh, A-Reum;Koh, Ba-Ra-Da;Jung, Bo-Ram;Na, Ho-Myoung;Bae, Seong-Yeol;Kim, Yong-Hwan
    • Korean Journal of Veterinary Service
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    • v.44 no.1
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    • pp.27-33
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    • 2021
  • Q fever is a worldwide zoonotic disease caused by Coxiella burnetii. Domestic ruminants are considered to be major source of human infection. The aim of this survey was to investigate seroprevalence of C. burnetii in ruminants in Gwangju area. A total of 1,000 samples (serum and lactoserum) were collected from 987 Korean native cattle, 5 Korean native goats, 2 beef cattle, 6 bulk-tank milk from each dairy farm in Gwangju area from January to October 2020 and analyzed by ELISA. The seroprevalence of C. burnetii in bulk-tank milk from each dairy farms was 50.0%. Korean black goat and beef cattle had negative antibody test results for C. burnetii. The seroprevalence of C. burnetii in Korean native cattle in Gwangju area was 7.1% and was higher in female (7.8%) than in male (3.4%) (P=0.024). The seroprevalence of C. burnetii in Korean native cattle appeared to increase with age (3.8% in 1 year-old, 7.1% in 3 year-old, and 10.7% in more than 5 year-old) (P<0.001). The seroprevalence of C. burnetii of Korean native cattle increased in spring and May was the highest in particular (P<0.001). As the distribution and density of tick-habitat are expected to increase due to climate crisis, this survey highlights the need for monitoring C. burnetii in domestic ruminants, including surveillance of C. burnetii infection in people working for livestock industry.

A study on AC-powered LED driver IC (교류 구동 LED 드라이버 IC에 관한 연구)

  • Jeon, Eui-Seok;An, Ho-Myoung;Kim, Byungcheul
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.14 no.4
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    • pp.275-283
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    • 2021
  • In this study, a driver IC for an AC-powered LED that can be manufactured with a low voltage semiconductor process is designed and the performances of the driver IC were simulated. In order to manufacture a driver IC that operates directly at AC 220V, a semiconductor manufacturing process that satisfies a breakdown voltage of 500V or higher is required. A semiconductor manufacturing process for a high-voltage device requires a much higher manufacturing cost than a general semiconductor process for a low-voltage device. Therefore, the LED driver IC is designed in series so that it can be manufactured with semiconductor process technology that implements a low-voltage device. This makes it possible to divide and apply the voltage to each LED block even if the input voltage is high. The LED lighting circuit shows a power factor of 96% at 220V. In the pnp transistor circuit, a very high power factor of 99.7% can be obtained, and it shows a very stable operation regardless of the fluctuation of the input voltage.