• Title/Summary/Keyword: 합성 알고리즘

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Vessel Detection Using Satellite SAR Images and AIS Data (위성 SAR 영상과 AIS을 활용한 선박 탐지)

  • Lee, Kyung-Yup;Hong, Sang-Hoon;Yoon, Bo-Yeol;Kim, Youn-Soo
    • Journal of the Korean Association of Geographic Information Studies
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    • v.15 no.2
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    • pp.103-112
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    • 2012
  • We demonstrate the preliminary results of ship detection application using synthetic aperture radar (SAR) and automatic identification system (AIS) together. Multi-frequency and multi-temporal SAR images such as TerraSAR-X and Cosmo-SkyMed (X-band), and Radarsat-2 (C-band) are acquired over the West Sea in South Korea. In order to compare with SAR data, we also collected an AIS data. The SAR data are pre-processed considering by the characteristics of scattering mechanism as for sea surface. We proposed the "Adaptive Threshold Algorithm" for classification ship efficiently. The analyses using the combination of the SAR and AIS data with time series will be very useful to ship detection or tracing of the ship.

A High Speed FFT Processor for OFDM Systems (OFDM 시스템을 위한 고속 FFT 프로세서)

  • 조병각;손병수;선우명훈
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.39 no.12
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    • pp.513-519
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    • 2002
  • This paper proposes a high-speed FFT processor for orthogonal frequency-division multiplexing(OFDM) systems. The Proposed architecture uses a single-memory architecture and uses a radix-4 algorithm for high speed. The proposed memory is partitioned into four banks for high-speed computation. It uses an in-place memory strategy that stores butterfly outputs in the same memory location used by butterfly inputs. Therefore, the memory size can be reduced. The SQNR of about 80dB is achieved with 20-bit input and 20-bit twiddle factors. The architecture has been modeled by VHDL and logic synthesis has been performed using the SamsungTM 0.5㎛ SOG cell library (KG80). The implemented FFT processor consists of 98,326 gates excluding memory. It has smaller hardware than existing pipeline FFT processors for more than 1024-point FFTs. The processor can operate at 42MHz and calculate a 256-point complex FFT in 6us. It satisfies tile required processing speed of 8.4㎲ in the HomePlug standard.

Implementation of ARM based Embedded System for Muscular Sense into both Color and Sound Conversion (근감각-색·음 변환을 위한 ARM 기반 임베디드시스템의 구현)

  • Kim, Sung-Ill
    • The Journal of the Korea Contents Association
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    • v.16 no.8
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    • pp.427-434
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    • 2016
  • This paper focuses on a real-time hardware processing by implementing the ARM Cortex-M4 based embedded system, using a conversion algorithm from a muscular sense to both visual and auditory elements, which recognizes rotations of a human body, directional changes and motion amounts out of human senses. As an input method of muscular sense, AHRS(Attitude Heading Reference System) was used to acquire roll, pitch and yaw values in real time. These three input values were converted into three elements of HSI color model such as intensity, hue and saturation, respectively. Final color signals were acquired by converting HSI into RGB color model. In addition, Three input values of muscular sense were converted into three elements of sound such as octave, scale and velocity, which were synthesized to give an output sound using MIDI(Musical Instrument Digital Interface). The analysis results of both output color and sound signals revealed that input signals of muscular sense were correctly converted into both color and sound in real time by the proposed conversion method.

Design of SAR Satellite Constellation Configuration for ISR Mission (ISR 임무를 위한 SAR 위성의 군집궤도 배치형상 설계)

  • Kim, Hongrae;Song, Sua;Chang, Young-Keun
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.45 no.1
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    • pp.54-62
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    • 2017
  • For the Earth observation satellite for ISR mission, a satellite constellation can be utilized to observe a specific area periodically and ultimately increase the effectiveness of the mission. The Walker-Delta method was applied to design constellation orbits with four satellites, which could detect abnormal activities in AoI(Area of Interest). To evaluate the effectiveness of the mission, a revisiting time was selected as a key requirement. This paper presents the mission analysis process for four SAR satellites constellation as well as the result of constellation configuration design to meet the requirements. Figure of Merits analysis was performed based on algorithm developed. Finally, it was confirmed that the constellation orbit with four different orbital planes is likely to be appropriate for ISR mission.

Computer Generated Hologram for Beam Control of LCOS based Wavelength Selective Switch (LCOS기반의 파장선택스위치 빔제어용 컴퓨터 생성 홀로그램)

  • Lee, Yong-Min;Han, Chang Ho
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.6
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    • pp.744-749
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    • 2016
  • This paper presents the design of a computer-generated hologram for beam control of an LCOS-based wavelength selective switch, which is the core technology for next-generation ROADM. By introducing a computer-generated hologram instead of general grating patterns to control the LCOS device, we contribute to building a more efficient wavelength selective switch. With the use of phase modulation properties of LCOS devices, we designed the hologram for five-port output and a 40-channel wavelength selective switch. We applied a multi-level phase modulation technique with the Gerchberg-Saxton algorithm to produce the hologram, which is easily scalable to any different type of wavelength selective switch. With an experimental setup, we verified the usability of the hologram designed for five-port output. We also suggest a hologram design technique for beam control of a 40-channel wavelength selective switch.

Pre-processing of Depth map for Multi-view Stereo Image Synthesis (다시점 영상 합성을 위한 깊이 정보의 전처리)

  • Seo Kwang-Wug;Han Chung-Shin;Yoo Ji-Sang
    • Journal of Broadcast Engineering
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    • v.11 no.1 s.30
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    • pp.91-99
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    • 2006
  • Pre-processing is one of image processing techniques to enhance image quality or appropriately convert a given image into another form for a specific purpose. An 8 bit depth map obtained by a depth camera usually contains a lot of noisy components caused by the characteristics of depth camera and edges are also more distorted by the quality of a source object and illumination condition comparing with edges in RGB texture image. To reduce this distortion, we use noise removing filters, but they are only able to reduce noise components, so that distorted edges of depth map can not be properly recovered. In this paper, we propose an algorithm that can reduce noise components and also enhance the quality of edges of depth map by using edges in RGB texture. Consequently, we can reduce errors in multi-view stereo image synthesis process.

Defect Inspection of FPD Panel Based on B-spline (B-spline 기반의 FPD 패널 결함 검사)

  • Kim, Sang-Ji;Hwang, Yong-Hyeon;Lee, Byoung-Gook;Lee, Joon-Jae
    • Journal of Korea Multimedia Society
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    • v.10 no.10
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    • pp.1271-1283
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    • 2007
  • To detect defect of FPD(flat panel displays) is very difficult due to uneven illumination on FPD panel image. This paper presents a method to detect various types of defects using the approximated image of the uneven illumination by B-spline. To construct a approximated surface, corresponding to uneven illumination background intensity, while reducing random noises and small defect signal, only the lowest smooth subband is used by wavelet decomposition, resulting in reducing the computation time of taking B-spline approximation and enhancing detection accuracy. The approximated image in lowest LL subband is expanded as the same size as original one by wavelet reconstruction, and the difference between original image and reconstructed one becomes a flat image of compensating the uneven illumination background. A simple binary thresholding is then used to separate the defective regions from the subtracted image. Finally, blob analysis as post-processing is carried out to get rid of false defects. For applying in-line system, the wavelet transform by lifting based fast algorithm is implemented to deal with a huge size data such as film and the processing time is highly reduced.

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Design of Time Synchronizer for Advanced LR-WPAN Systems (개선된 LR-WPAN 시스템을 위한 시간 동기부 설계)

  • Park, Mincheol;Lee, Dongchan;Jang, Soohyun;Jung, Yunho
    • Journal of Advanced Navigation Technology
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    • v.18 no.5
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    • pp.476-482
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    • 2014
  • Recently, with the growth of various sensor applications, the need of wireless communication systems which can support variable data rate is increasing. IEEE 802.15.4 LR-WPAN system using 2.45 GHz frequency band is very popular for the sensor applications. However, since LR-WPAN only supports the data rate of 250 kbps, it has a limit to be applied to various sensor networks. Therefore, we define the preamble structure which can support the data rates of 31.25 kbps, 62.5 kbps, 125 kbps, and present the low-complexity hardware architecture for time synchronizer based on double-correlation algorithm which can resist the CFO (carrier frequency offset). Implementation results show that the proposed time synchronizer include the logic slice of 18.36 K and four DSP48s, which are reduced at the rate of 79.1% and 99.4%, respectively, compared with existing architecture.

Effective hardware design for DCT-based Intra prediction encoder (DCT 기반 인트라 예측 인코더를 위한 효율적인 하드웨어 설계)

  • Cha, Ki-Jong;Ryoo, Kwang-Ki
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.4
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    • pp.765-770
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    • 2012
  • In this paper, we proposed an effective hardware structure using DCT-based inra-prediction mode selection to reduce computational complexity caused by intra mode decision. In this hardware structure, the input block is transformed at first and then analyzed to determine its texture directional tendency. the complexity has solved by performing intra prediction in only predicted edge direction. $4{\times}4$ DCT is calculated in one cycle using Multitransform_PE and Inta_pred_PE calculates one prediction mode in two cycles. Experimental results show that the proposed Intra prediction encoding needs only 517 cycles for one macroblock encoding. This architecture improves the performance by about 17% than previous designs. For hardware implementation, the proposed intra prediction encoder is implemented using Verilog HDL and synthesized with Megnachip $0.18{\mu}m$ standard cell library. The synthesis results show that the proposed architecture can run at 125MHz.

Design and Implementation of Time Synchronizer for Advanced ZigBee Systems (개선된 지그비 시스템을 위한 시간 동기부 설계 및 구현)

  • Hwang, Hyunsu;Jung, Yongcheol;Jung, Yunho
    • Journal of Advanced Navigation Technology
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    • v.20 no.5
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    • pp.453-461
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    • 2016
  • Recently, with the growth of various sensor applications, the need of wireless communication systems which can support variable data rate is increasing. Therefore, advanced ZigBee (AZB) systems that support the various data rate under 250 kbps are proposed. However, the preamble structure for AZB systems causes the complexity increase of time synchronization circuits. In this paper, we propose preamble structure and time synchronization algorithm which can solve the problem of the complexity increase of time synchronization circuits. Implementation results show that the proposed time synchronizer for AZB systems include the logic slices of 6.92 k and, which are reduced at the rate of 62.3% compared with existing architecture.